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器件型号：AFE7900EVM 您好！
最初、我可以使用 ZCU102_AFE79xx_8b10b_5Gbps_4Rx 中的示例来成功接收数据、使用2通道4rx。
但是、我将尝试 使用 fb 输入来接收数据。
我按如下方式修改了脚本。
setupParams.skipFpga = True # setup FPGA (TSW14J56) using HSDC Pro
############## Top Level ##############
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*3
sysParams.externalClockRx=False
sysParams.externalClockTx=False
############## Digital Chain ##############
##### RX #####
sysParams.rxEnable = [False,False,False,False]
sysParams.ddcFactorRx = [48]*4 #DDC decimation factor for RX A, B, C and D
sysParams.rxNco0 = [[5400,5400], #Band0, Band1 for RXA
[500,500], #Band0, Band1 for RXB
[2500,2500], #Band0, Band1 for RXC
[1800,1800]] #Band0, Band1 for RXD
##### FB #####
sysParams.fbEnable = [True,True]
sysParams.ddcFactorFb = [24,24] #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [500,1800] #Band0 for FB1 and FB2
##### TX #####
sysParams.txEnable = [False,False,False,False]
sysParams.ducFactorTx = [18]*4 #DUC interpolation factor for TX A, B, C and D
sysParams.txNco0 = [[5400,5400], #Band0, Band1 for TXA
[500,500], #Band0, Band1 for TXB
[2500,2500], #Band0, Band1 for TXC
[1800,1800]] #Band0, Band1 for TXD
############## JESD ##############
##### ADC-JESD #####
#sysParams.jesdSystemMode= [3,3]
sysParams.jesdSystemMode= [4,4]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb
#SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx -rx -rx -rx
#SystemMode 4: 1F ; fb -fb- fb -fb
#SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb
sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["14810","14810","14810","14810"] #2LANE
#sysParams.LMFSHdRx = ["28810","28810","28810","28810"]
# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["12410","12410"]
sysParams.rxJesdTxScr = [True,True,True,True]
sysParams.fbJesdTxScr = [True,True]
sysParams.rxJesdTxK = [16,16,16,16]
sysParams.fbJesdTxK = [16,16]
sysParams.jesdTxLaneMux = [5,1,2,3,0,4,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2T,
# this should be [[1,0,2,3],[5,4,6,7]]
##### JESD Common #####
sysParams.jesdABLvdsSync= False
sysParams.jesdCDLvdsSync= False
sysParams.syncLoopBack = True #JESD Sync signal is connected to FPGA
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'DAC_SYNC0',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'ADC_SYNC1',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
############## LMK Params ##############
#lmkParams.pllEn = False
#lmkParams.inputClk = 983.04 # Valid only when lmkParams.pllEn = False
#lmkParams.lmkFrefClk = True
#setupParams.fpgaRefClk = 61.44 # Should be equal to LaneRate/40 for TSW14J56
lmkParams.pllEn = True#False
lmkParams.inputClk = 1474.56#737.28
lmkParams.sysrefFreq = 2949.12/1024 # check 2.88
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 122.88
#setupParams.fpgaRefClk = 61.44 # Should be equal to LaneRate/40 for TSW14J56
############## Logging ##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
lmk.rawWriteLogEn = 1
setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()
您知道为什么我无法接收 数据吗？ 你觉得脚本有什么问题吗？"
fb 通道是否有示例工作脚本或示例？
非常感谢。
此致、
