TI E2E 英文论坛海量技术问答的中文版全新上线,可点击相关论坛查看,或在站内搜索 “参考译文” 获取。

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[参考译文] CC2538EMK:使用 CCA 阈值降低接收范围/灵敏度

Other Parts Discussed in Thread: CC2538, CC2538EMK, Z-STACK
请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/wireless-connectivity/zigbee-thread-group/zigbee-and-thread/f/zigbee-thread-forum/1086325/cc2538emk-decreasing-the-receiving-range-sensitivity-using-cca-threshold

部件号:CC2538EMK
“线程”中讨论的其它部件:CC2538Z 堆栈,测试

我正在尝试降低 节点的接收器灵敏度。   在这里建议 我 重点关注 CCA 阈值,以便能够做到这一点。 但问题是,即使我 使用 RFCORE_XREG_CCACTRL0 = 0x35设置了阈值(例如-20),知道  CC2538_RSSI_OFFSET 是-73,设备仍会获得 RSSI 低于-20的数据包(例如 -76)。即不会发生任何变化。 我还尝试了4种 CCA 模式(0,1,2,3),但仍然相同。

我正在使用不同的固件(安装在 Openmote-CC2538,CC2538EMK 设备中的 RIOT 操作系统),我确信要使 CCA 值发挥作用的不仅仅是设置正确的值,如设置 RFCORE_XREG_RFC_OBS_OBS_CTR0/1。 我还尝试在  Zigbee 固件中映射设置 ,但无法成功启用 CCA。

我非常感谢你就此事提供的意见。

以下是防暴操作系统中 CC2538模块的一些代码/定义,供您参考:

cc2538-rf.h

/**
 * @brief Values for use with CCTEST_OBSSELx registers.
 */
enum {
    rfc_obs_sig0 = 0,
    rfc_obs_sig1 = 1,
    rfc_obs_sig2 = 2,
};

/**
 * @brief Values for RFCORE_XREG_RFC_OBS_CTRLx registers.
 */
enum {
    constant_value_0 = 0x00, /**< Constant value 0 */
    constant_value_1 = 0x01, /**< Constant value 1*/
    rfc_sniff_data   = 0x08, /**< Data from packet sniffer. Sample data
                                  on rising edges of sniff_clk.*/
    rfc_sniff_clk    = 0x09, /**< 250kHz clock for packet sniffer data.*/
    rssi_valid       = 0x0c, /**< Pin is high when the RSSI value has
                                  been updated at least once since RX was
                                  started. Cleared when leaving RX.*/
    demod_cca        = 0x0d, /**< Clear channel assessment. See FSMSTAT1
                                  register for details on how to configure
                                  the behavior of this signal. */
    sampled_cca      = 0x0e, /**< A sampled version of the CCA bit from
                                  demodulator. The value is updated whenever
                                  a SSAMPLECCA or STXONCCA strobe is issued.*/
    sfd_sync         = 0x0f, /**< Pin is high when a SFD has been received
                                  or transmitted. Cleared when leaving
                                  RX/TX respectively. Not to be confused
                                  with the SFD exception.*/
    tx_active        = 0x10, /**< Indicates that FFCTRL is in one of the TX
                                  states. Active-high.*/
    rx_active        = 0x11, /**< Indicates that FFCTRL is in one of the
                                  RX states. Active-high. */
    ffctrl_fifo      = 0x12, /**< Pin is high when one or more bytes are
                                  in the RXFIFO. Low during RXFIFO overflow. */
    ffctrl_fifop     = 0x13, /**< Pin is high when the number of bytes
                                  in the RXFIFO exceeds the programmable
                                  threshold or at least  one complete
                                  frame is in the RXFIFO. Also highduring
                                  RXFIFO overflow. Not to be confused with
                                  the FIFOP exception.*/
    packet_done      = 0x14, /**< A complete frame has been received.
                                  I.e., the number of bytes set by the
                                  frame-length field has been received.*/
    rfc_xor_rand_i_q = 0x16, /**< XOR between I and Q random outputs.
                                  Updated at 8 MHz.*/
    rfc_rand_q       = 0x17, /**< Random data output from the Q channel
                                  of the receiver. Updated at 8 MHz.*/
    rfc_rand_i       = 0x18, /**< Random data output from the I channel
                                  of the receiver. Updated at 8 MHz */
    lock_status      = 0x19, /**< 1 when PLL is in lock, otherwise 0 */
    pa_pd            = 0x20, /**< Power amplifier power-down signal */
    lna_pd           = 0x2a, /**< LNA power-down signal*/
    disabled         = 0xff, /**< disabled */
};


/**
 * @name    RF CORE observable signals settings
 */
#ifndef CONFIG_CC2538_RF_OBS_0
#define CONFIG_CC2538_RF_OBS_0      tx_active
#endif
#ifndef CONFIG_CC2538_RF_OBS_1
#define CONFIG_CC2538_RF_OBS_1      rx_active
#endif
#ifndef CONFIG_CC2538_RF_OBS_2
#define CONFIG_CC2538_RF_OBS_2      rssi_valid
#endif

/* Default configuration for cc2538dk or similar */
#ifndef CONFIG_CC2538_RF_OBS_SIG_0_PCX
#define CONFIG_CC2538_RF_OBS_SIG_0_PCX  0   /* PC0 = LED_1 (red) */
#endif
#ifndef CONFIG_CC2538_RF_OBS_SIG_1_PCX
#define CONFIG_CC2538_RF_OBS_SIG_1_PCX  1   /* PC0 = LED_2 (red) */
#endif
#ifndef CONFIG_CC2538_RF_OBS_SIG_2_PCX
#define CONFIG_CC2538_RF_OBS_SIG_2_PCX  2   /* PC0 = LED_3 (red) */
#endif
#if ((CONFIG_CC2538_RF_OBS_SIG_2_PCX > 7) || \
     (CONFIG_CC2538_RF_OBS_SIG_1_PCX > 7) || \
     (CONFIG_CC2538_RF_OBS_SIG_0_PCX > 7))
#error "CONFIG_CC2538_RF_OBS_SIG_X_PCX must be between 0-7 (PC0-PC7)"
#endif

cc2538-RF.c.

/**
 * @name    RF CORE observable signals settings
 * @{
 */
#define CONFIG_CC2538_RF_OBS_SIG_0_PCX  5   /* PC5 */
#define CONFIG_CC2538_RF_OBS_SIG_1_PCX  6   /* PC6 */
#define CONFIG_CC2538_RF_OBS_SIG_2_PCX  7   /* PC7 */
/** @} */

static void _cc2538_observable_signals(void)
{
    /* Select on which pin PC0:7 should the selected observable signals
       be wired through, the signal is selected in CONFIG_CC2538_RF_OBS_%
       and the pin in CONFIG_CC2538_RF_OBS_SIG_%_PCX */
    if (IS_USED(MODULE_CC2538_RF_OBS_SIG)) {
        if (CONFIG_CC2538_RF_OBS_0 != disabled) {
            RFCORE_XREG_RFC_OBS_CTRL0 = CONFIG_CC2538_RF_OBS_0;
            *(&CCTEST_OBSSEL0 + CONFIG_CC2538_RF_OBS_SIG_0_PCX) = \
                CCTEST_OBSSELX_EN | rfc_obs_sig0;
        }
        if (CONFIG_CC2538_RF_OBS_1 != disabled) {
            RFCORE_XREG_RFC_OBS_CTRL1 = CONFIG_CC2538_RF_OBS_1;
            *(&CCTEST_OBSSEL0 + CONFIG_CC2538_RF_OBS_SIG_1_PCX) = \
                CCTEST_OBSSELX_EN | rfc_obs_sig1;
        }
        if (CONFIG_CC2538_RF_OBS_2 != disabled) {
            RFCORE_XREG_RFC_OBS_CTRL2 = CONFIG_CC2538_RF_OBS_2;
            *(&CCTEST_OBSSEL0 + CONFIG_CC2538_RF_OBS_SIG_2_PCX) = \
                CCTEST_OBSSELX_EN | rfc_obs_sig2;
        }
    }
}


void cc2538_init(void)
{
    /* Enable RF CORE clock in active mode */
    SYS_CTRL_RCGCRFC = 1UL;
    /* Enable  RF CORE  clock in sleep mode */
    SYS_CTRL_SCGCRFC = 1UL;
    /* Enable  RF CORE  clock in PM0 (system clock always powered down
        in PM1-3) */
    SYS_CTRL_DCGCRFC = 1UL;
    /* Wait for the clock enabling to take effect */
    while (!(SYS_CTRL_RCGCRFC & 1UL) || \
           !(SYS_CTRL_SCGCRFC & 1UL) || \
           !(SYS_CTRL_DCGCRFC & 1UL)
           ) {}

    /* Register Setting updates for optimal performance, RM section 23.15 */
    RFCORE_XREG_TXFILTCFG   = 0x09;
    RFCORE_XREG_AGCCTRL1    = 0x15;
    RFCORE_XREG_FSCAL1      = 0x01;
    ANA_REGS_IVCTRL         = 0x0B;

    /* Enable AUTOCRC and AUTOACK by default*/
    RFCORE_XREG_FRMCTRL0   = AUTOCRC | AUTOACK;

    /* Disable RX after TX, let upper layer change the state */
    RFCORE_XREG_FRMCTRL1 = 0x00;

    /* Disable source address matching and pending bits */
    RFCORE_XREG_SRCMATCH = 0x00;

    /* Set FIFOP_THR to its max value*/
    RFCORE_XREG_FIFOPCTRL = CC2538_RF_MAX_DATA_LEN;

    /* Set default IRQ */
    cc2538_rf_enable_irq();

    /* Enable all RF CORE error interrupts */
    RFCORE_XREG_RFERRM = STROBE_ERR | TXUNDERF | TXOVERF | \
                         RXUNDERF | RXOVERF | NLOCK;

    _cc2538_observable_signals();

    #ifdef CC2592_EMBEDDED
        #if (CC2592_EMBEDDED == 1)
            RFCORE_XREG_RFC_OBS_CTRL0 = 0x6A; //0x20; //0x6A;
            RFCORE_XREG_RFC_OBS_CTRL1 = 0x68; //0x2a; //0x68;
        #else
            RFCORE_XREG_RFC_OBS_CTRL0 = 0x20; //0x20; //0x6A;
            RFCORE_XREG_RFC_OBS_CTRL1 = 0x2a; //0x2a; //0x68;
        #endif
        CCTEST_OBSSEL2 = 0x80;
        CCTEST_OBSSEL3 = 0x81;    
    #endif

    /* Remaingin Code... */
    
}

使用 openmode-cc2538时,以下寄存器通常具有以下值

RFCORE_XREG_RFC_OBS_CTRL0 = 0x10;
RFCORE_XREG_RFC_OBS_CTRL1 = 0x11;

我尝试将它们更改为以下以实现 CCA:

RFCORE_XREG_RFC_OBS_CTRL0 = 0x10;
RFCORE_XREG_RFC_OBS_CTRL1 = 0x0d;  // also 0x0e

请提供帮助,

艾哈迈德

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你好,Ahed,

    您可以查看 TRM 以了解有关这些寄存器的更多信息。  在 Z-Stack 和 RF 示例中,我只见 过 RFC_OBS_CTRL0/1被修改以控制射频前端芯片的信号。  您还可以参考 CC2538-SW (包括每次测试),以更好地了解如何通过 CCACTRLX 寄存器设置 CCA_THR。   最好让 Contiki 社区解决您的第三方软件问题

    此致,
    瑞安