[参考译文] CC2652R：线程 SED 电流消耗

[引用 userid="373585" URL"~/support/wireless-connectivity/zigbee-thread-group/zigbee-and-thread/f/zigbee-thread-forum/1000398/cc2652r-thread-sed-current-consumption/3696657 #3696657"]但我可以排除硬件错误，因为它在以前的测试中已经使用过此硬件。

为了帮助我在此处了解、请执行以下操作：

• 这是否意味着您已经测量了此定制 PCB 的预期低电流消耗？
  • 如果是，您能否共享这是哪个 SDK (如果不是5.10)？
• 您是否尝试运行简单的待机示例(设备仅休眠、未启用外设)？

检查我末尾的寄存器、我确实看到 crypto_clk_EN = 1、但 Periph_on = 0。
您能否共享寄存器的快照？ (PRCM 类别目前应已足够)。
这就是我在结尾看到的内容：

PRCM	Power, Reset and Clock Management	
	INFRCLKDIVR	0x00000000	Infrastructure Clock Division Factor For Run Mode [Memory Mapped]	
	INFRCLKDIVS	0x00000000	Infrastructure Clock Division Factor For Sleep Mode [Memory Mapped]	
	INFRCLKDIVDS	0x00000000	Infrastructure Clock Division Factor For DeepSleep Mode [Memory Mapped]	
	VDCTL	0x00000001	MCU Voltage Domain Control [Memory Mapped]	
	CLKLOADCTL	0x00000002	Load PRCM Settings To CLKCTRL Power Domain [Memory Mapped]	
	RFCCLKG	0x00000001	RFC Clock Gate [Memory Mapped]	
	VIMSCLKG	0x00000003	VIMS Clock Gate [Memory Mapped]	
	SECDMACLKGR	0x00000001	SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes [Memory Mapped]	
	SECDMACLKGS	0x00000001	SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode [Memory Mapped]	
	SECDMACLKGDS	0x00000000	SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode [Memory Mapped]	
	GPIOCLKGR	0x00000001	GPIO Clock Gate For Run And All Modes [Memory Mapped]	
	GPIOCLKGS	0x00000001	GPIO Clock Gate For Sleep Mode [Memory Mapped]	
	GPIOCLKGDS	0x00000001	GPIO Clock Gate For Deep Sleep Mode [Memory Mapped]	
	GPTCLKGR	0x00000000	GPT Clock Gate For Run And All Modes [Memory Mapped]	
	GPTCLKGS	0x00000000	GPT Clock Gate For Sleep Mode [Memory Mapped]	
	GPTCLKGDS	0x00000000	GPT Clock Gate For Deep Sleep Mode [Memory Mapped]	
	I2CCLKGR	0x00000000	I2C Clock Gate For Run And All Modes [Memory Mapped]	
	I2CCLKGS	0x00000000	I2C Clock Gate For Sleep Mode [Memory Mapped]	
	I2CCLKGDS	0x00000000	I2C Clock Gate For Deep Sleep Mode [Memory Mapped]	
	UARTCLKGR	0x00000001	UART Clock Gate For Run And All Modes [Memory Mapped]	
	UARTCLKGS	0x00000001	UART Clock Gate For Sleep Mode [Memory Mapped]	
	UARTCLKGDS	0x00000001	UART Clock Gate For Deep Sleep Mode [Memory Mapped]	
	SSICLKGR	0x00000000	SSI Clock Gate For Run And All Modes [Memory Mapped]	
	SSICLKGS	0x00000000	SSI Clock Gate For Sleep Mode [Memory Mapped]	
	SSICLKGDS	0x00000000	SSI Clock Gate For Deep Sleep Mode [Memory Mapped]	
	I2SCLKGR	0x00000000	I2S Clock Gate For Run And All Modes [Memory Mapped]	
	I2SCLKGS	0x00000000	I2S Clock Gate For Sleep Mode [Memory Mapped]	
	I2SCLKGDS	0x00000000	I2S Clock Gate For Deep Sleep Mode [Memory Mapped]	
	SYSBUSCLKDIV	0x00000000	Internal. Only to be used through TI provided API. [Memory Mapped]	
	CPUCLKDIV	0x00000000	Internal. Only to be used through TI provided API. [Memory Mapped]	
	PERBUSCPUCLKDIV	0x00000000	Internal. Only to be used through TI provided API. [Memory Mapped]	
	PERBUSDMACLKDIV	0x00000000	Internal. Only to be used through TI provided API. [Memory Mapped]	
	PERDMACLKDIV	0x00000000	Internal. Only to be used through TI provided API. [Memory Mapped]	
	I2SBCLKSEL	0x00000000	I2S Clock Control [Memory Mapped]	
	GPTCLKDIV	0x00000000	GPT Scalar [Memory Mapped]	
	I2SCLKCTL	0x00000000	I2S Clock Control [Memory Mapped]	
	I2SMCLKDIV	0x00000000	MCLK Division Ratio [Memory Mapped]	
	I2SBCLKDIV	0x00000000	BCLK Division Ratio [Memory Mapped]	
	I2SWCLKDIV	0x00000000	WCLK Division Ratio [Memory Mapped]	
	RESETSECDMA	0x00000000	RESET For SEC (PKA And TRNG And CRYPTO) And UDMA [Memory Mapped]	
	RESETGPIO	0x00000000	RESET For GPIO IPs [Memory Mapped]	
	RESETGPT	0x00000000	RESET For GPT Ips [Memory Mapped]	
	RESETI2C	0x00000000	RESET For I2C IPs [Memory Mapped]	
	RESETUART	0x00000000	RESET For UART IPs [Memory Mapped]	
	RESETSSI	0x00000000	RESET For SSI IPs [Memory Mapped]	
	RESETI2S	0x00000000	RESET For I2S IP [Memory Mapped]	
	PDCTL0	0x00000000	Power Domain Control [Memory Mapped]	
	PDCTL0RFC	0x00000000	RFC Power Domain Control [Memory Mapped]	
	PDCTL0SERIAL	0x00000000	SERIAL Power Domain Control [Memory Mapped]	
	PDCTL0PERIPH	0x00000000	PERIPH Power Domain Control [Memory Mapped]	
	PDSTAT0	0x00000000	Power Domain Status [Memory Mapped]	
	PDSTAT0RFC	0x00000000	RFC Power Domain Status [Memory Mapped]	
	PDSTAT0SERIAL	0x00000000	SERIAL Power Domain Status [Memory Mapped]	
	PDSTAT0PERIPH	0x00000000	PERIPH Power Domain Status [Memory Mapped]	
	PDCTL1	0x00000000	Power Domain Control [Memory Mapped]	
	PDCTL1CPU	0x00000000	CPU Power Domain Direct Control [Memory Mapped]	
	PDCTL1RFC	0x00000000	RFC Power Domain Direct Control [Memory Mapped]	
	PDCTL1VIMS	0x00000000	VIMS Mode Direct Control [Memory Mapped]	
	PDSTAT1	0x0000001A	Power Manager Status [Memory Mapped]	
	PDSTAT1BUS	0x00000001	BUS Power Domain Direct Read Status [Memory Mapped]	
	PDSTAT1RFC	0x00000000	RFC Power Domain Direct Read Status [Memory Mapped]	
	PDSTAT1CPU	0x00000001	CPU Power Domain Direct Read Status [Memory Mapped]	
	PDSTAT1VIMS	0x00000001	VIMS Mode Direct Read Status [Memory Mapped]	
	RFCBITS	0xE0000091	Control To RFC [Memory Mapped]	
	RFCMODESEL	0x00000000	Selected RFC Mode [Memory Mapped]	
	RFCMODEHWOPT	0x0000000F	Allowed RFC Modes [Memory Mapped]	
	PWRPROFSTAT	0x00000000	Power Profiler Register [Memory Mapped]	
	MCUSRAMCFG	0x00000020	MCU SRAM configuration [Memory Mapped]	
	RAMRETEN	0x00000008	Memory Retention Control [Memory Mapped]	
	OSCIMSC	0x00000000	Oscillator Interrupt Mask [Memory Mapped]	
	OSCRIS	0x000000FB	Oscillator Raw Interrupt Status [Memory Mapped]	
	OSCICR	0x00000000	Oscillator Raw Interrupt Clear [Memory Mapped]	

您还能描述测试期间的整体网络流量吗？
例如、SED 发送/接收数据包的频率。

我的测试设置相对简单-- SED 每2秒轮询一次，每10秒发送一次报告。

您好！

我们已经找到了问题。 我使用另一个 MCU 在类似电路板上测量了低电流。 然后、我尝试使用空示例来确保 MCU 真正处于深度睡眠状态、然后再在软件方面取得任何进一步进展。 简而言之、我们认识到、与旧 PCB 相比、该 PCB 上还放置了两个附加组件。 删除它们可以解决问题。

解决该问题后、我可以在示波器上看到器件在启动时没有休眠几秒钟、但随后睡眠很好。 这也意味着正确的是、某些时钟在启动后不久仍会在时间点激活。

尽管如此、感谢您的提示和帮助！