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TMS320F28P550SJ: 参考电压问题

zp yang
Prodigy 20 points
Part Number: TMS320F28P550SJ


1.使用3.3V供电，ADC使用内部参考电压3.3V基准，在VREFHi引脚测量到，1.65V电压有200mv的纹波。需要改进那个方面

2.尝试使用外部参考模式在VREFHI引脚接入3.3V，选择外部基准模式，但是对1.65V的信号采样结果是0.82V。这个是什么原因导致。

3.1.2V是来自于芯片内部LDO还是说需要外部供电1.2V。什么情况下需要外部供电。

以上问题请帮忙提供思路和解决方案。

 

  1. With a 3.3V power supply and the ADC using an internal 3.3V reference voltage, a 1.65V signal measured at the VREFHi pin exhibits a 200mV ripple. Which aspect needs improvement?

  2. When attempting to use external reference mode by connecting 3.3V to the VREFHi pin and selecting external reference mode, the sampled result for a 1.65V input signal is 0.82V. What could be causing this issue?

  3. Is the 1.2V supplied by an internal LDO within the chip, or does it require an externally provided 1.2V supply? Under what circumstances is an external 1.2V supply necessary?

Please provide guidance and solutions for the above issues.

  • 0
    TI__Mastermind 32135 points

    Hello, we have received your case and the investigation will take some time. Thank you for your patience.

  • 0 回复 Eirwen
    TI__Mastermind 32135 points

    This ripple almost always points to reference decoupling and analog supply integrity. I suggest to check the VDDA/VSSA cleanliness. Keep VDDA well-decoupled (local bulk pluse high-frequency caps) and avoid sharing high di/dt digital return paths with VSSA. Alos, note that scope probing by a long ground lead can easily cause 200 mV ripple. You should measure this with a spring ground right at the pins before changing hardware.

    In external reference mode, your symptom is a near-perfect “/2” error. If you drive VREFHI = 3.3 V, and leave x2 scaling enabled (ANAREFx1P65SEL = 1), then the ADC effectively behaves as if full-scale is 6.6 V, so a 1.65 V input lands at around 25% FS which many users then interpret as 0.825 V when converting back to volts. Here you can disable the x2 (1.65*2) scaling.

    Regarding 1.2 V rail, most designs can run single-rail 3.3 V and let the internal VREG generate the 1.2 V rail. If your application requires VDD (1.2 V) monitoring with an external supervisor, using an external supervisor with the internal VREG is not supported; in that case you should power VDD externally (requires a package with VREGENZ).