TMS320F280049: F280049 EPWM2有概率无法正常输出

Part Number: TMS320F280049

EPWM2与EPWM1同步,且移相180°,频率100KHz,每次启动的时候,EPWM2有时候会无法正常输出:A常高,B常低,重新启动也是不行,改成别的频率65KHz,又恢复正常了占空比输出,这可能是哪里的问题呢?

启动方式:

            EPwm1Regs.TZCLR.bit.OST = 1;

            EPwm1Regs.TZCLR.bit.INT = 1;

            EPwm2Regs.TZCLR.bit.OST = 1;

            EPwm2Regs.TZCLR.bit.INT = 1;

停止方式:

            EPwm1Regs.TZFRC.bit.OST = 1;

            EPwm2Regs.TZFRC.bit.OST = 1;

以下是EPWM的配置:

    EPwm1Regs.TBPRD = 999;

    EPwm1Regs.CMPA.bit.CMPA = 332;         

    EPwm1Regs.TBPHS.bit.TBPHS = 0;

    EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP;                         

    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;                             

    EPwm1Regs.TBCTL.bit.CLKDIV = 0;           

    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;

    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;                              

    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;

    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;                    

    //Init duty control register;

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //Set action

    EPwm1Regs.AQCTLA.all=0x0000;

    EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;

    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    //init software force register;

    EPwm1Regs.AQSFRC.bit.RLDCSF = 2;                                

    EPwm1Regs.AQSFRC.bit.ACTSFB = 0;                                

    EPwm1Regs.AQSFRC.bit.ACTSFA = 0;                                

    EPwm1Regs.AQCSFRC.bit.CSFA = 0;                                 

    EPwm1Regs.AQCSFRC.bit.CSFB = 0;                                 

    //Init deadband register;

    EPwm1Regs.DBCTL.bit.SHDWDBFEDMODE = 1;                          

    EPwm1Regs.DBCTL.bit.SHDWDBREDMODE = 1;                          

    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;                          

    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;                

    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;                

    EPwm1Regs.DBFED.bit.DBFED = 30;

    EPwm1Regs.DBRED.bit.DBRED = 30;

    //Init PWM interrupt;

    EPwm1Regs.ETSEL.bit.INTEN = 0;

    //Init AD trig;

    EPwm1Regs.ETSEL.bit.SOCAEN = 0;

    EPwm1Regs.ETSEL.bit.SOCBEN = 0;

    //Init TZ

    EALLOW;

    EPwm1Regs.TZSEL.all = 0x0000;

    EPwm1Regs.TZSEL.bit.OSHT1 = 1;

    EPwm1Regs.TZSEL.bit.OSHT2 = 1;

    EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;                         

    EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;                         

    EPwm1Regs.TZCLR.bit.OST = 1;

    EPwm1Regs.TZCLR.bit.INT = 1;

    EPwm1Regs.TZEINT.bit.OST = 0;

    EPwm1Regs.TZFRC.bit.OST = 1;

    //Init chop;

    EPwm1Regs.PCCTL.bit.CHPEN = CHP_DISABLE;

    EDIS;

 

    EPwm2Regs.TBPRD = 999;

    EPwm2Regs.CMPA.bit.CMPA = 332;         

    EPwm2Regs.TBPHS.bit.TBPHS = 499;

    EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;                         

    EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;                             

    EPwm2Regs.TBCTL.bit.CLKDIV = 0;           

    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;

    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;                              

    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;

    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;                    

    //Init duty control register;

    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //Set action

    EPwm2Regs.AQCTLA.all=0x0000;

    EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET;

    EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    //init software force register;

    EPwm2Regs.AQSFRC.bit.RLDCSF = 2;                                

    EPwm2Regs.AQSFRC.bit.ACTSFB = 0;                                

    EPwm2Regs.AQSFRC.bit.ACTSFA = 0;                                

    EPwm2Regs.AQCSFRC.bit.CSFA = 0;                                 

    EPwm2Regs.AQCSFRC.bit.CSFB = 0;                                 

    //Init deadband register;

    EPwm2Regs.DBCTL.bit.SHDWDBFEDMODE = 1;                          

    EPwm2Regs.DBCTL.bit.SHDWDBREDMODE = 1;                          

    EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;                          

    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;                

    EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;                

    EPwm2Regs.DBFED.bit.DBFED = 30;

    EPwm2Regs.DBRED.bit.DBRED = 30;

    //Init PWM interrupt;

    EPwm2Regs.ETSEL.bit.INTEN = 0;

    //Init AD trig;

    EPwm2Regs.ETSEL.bit.SOCAEN = 0;

    EPwm2Regs.ETSEL.bit.SOCBEN = 0;

    //Init TZ

    EALLOW;

    EPwm2Regs.TZSEL.all = 0x0000;

    EPwm2Regs.TZSEL.bit.OSHT1 = 1;

    EPwm2Regs.TZSEL.bit.OSHT2 = 1;

    EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;                         

    EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;                         

    EPwm2Regs.TZCLR.bit.OST = 1;

    EPwm2Regs.TZCLR.bit.INT = 1;

    EPwm2Regs.TZEINT.bit.OST = 0;

    EPwm2Regs.TZFRC.bit.OST = 1;