McBSP帧同步脉宽设置问题，无法设置低于字长的脉宽

静水流深

Prodigy 71 points

Other Parts Discussed in Thread: TMS320F28377S

芯片：TMS320F28377S

模块：McBSP

设置：

1、MCLKR引脚作为模块时钟，1.2KH，不分频

2、每10ms周期发送一次，8bit

3、时钟停止模式，不发数据时，CLKX高电平，无延时

4，帧同步信号脉宽2个CLKG时钟，FWID = 1

问题：

实测帧同步脉宽为9个时钟周期；

经测试，当FWID = 0-7时，帧同步脉宽都是9个时钟，这和描述不一样；

当FWID>7是，帧同步脉宽为[FWID+1]时钟，和描述一样。

经测试，采用内部LSPCLK时钟，问题一样。

初始化代码：

void McBSP_Init(void)
{
McbspaRegs.SPCR2.all=0x0000;
McbspaRegs.SPCR1.all=0x0000;

McbspaRegs.SPCR2.bit.FREE = 1;
McbspaRegs.SPCR2.bit.SOFT = 1; //1x - Free run
McbspaRegs.SPCR2.bit.XINTM = 0; //0 - XINT when XRDY set, indicate the transmitter is ready to accept new data
McbspaRegs.SPCR2.bit.XSYNCERR = 0; //0 - Clear Transmit frame-synch error

McbspaRegs.SPCR1.bit.DLB = 0; //0 - Disable DLB mode. Comment out for non-DLB mode.
McbspaRegs.SPCR1.bit.RJUST = 0; //0 - Right justify the Receive data and Zero fill the MSB
McbspaRegs.SPCR1.bit.CLKSTP = 0x2; //2 - Clock stop mode, without clock delay
McbspaRegs.SPCR1.bit.DXENA = 0; //0 - DX delay enabler off
McbspaRegs.SPCR1.bit.RINTM = 0; //0 - RINT when RRDY set, indicate the receive data is ready to be read
McbspaRegs.SPCR1.bit.RSYNCERR = 0; //0 - Clear Receive frame-synch error

McbspaRegs.MFFINT.all = 0x0; //0 - Disable all interrupts

McbspaRegs.RCR2.bit.RPHASE = 0; //0 - Single-phase frame
McbspaRegs.RCR2.bit.RCOMPAND = 0; //0 - No companding, MSB received first
McbspaRegs.RCR2.bit.RFIG = 1; //0 - Unexpected frame-synch cause aborts data,set RSYNCEERR and begin new data
McbspaRegs.RCR2.bit.RDATDLY = 0; //0 - RX data delay is 0 bit

McbspaRegs.RCR1.bit.RFRLEN1 = 0; //0 - 1 word in phase 1 of the receive frame
McbspaRegs.RCR1.bit.RWDLEN1 = 2; //2 - 16bits, Receive word length

McbspaRegs.XCR2.bit.XPHASE = 0; //0 - Single-phase frame
McbspaRegs.XCR2.bit.XCOMPAND = 0; //0 - No companding, MSB transmit first
McbspaRegs.XCR2.bit.XFIG = 1; //1 - Ignore Transmit Frame-synch
McbspaRegs.XCR2.bit.XDATDLY = 0; //0 - TX data delay is 0 bit

McbspaRegs.XCR1.bit.XFRLEN1 = 0; //0 - 1 word in phase 1 of the transmit frame
McbspaRegs.XCR1.bit.XWDLEN1 = 0; //0 - 8 bits, Transmit word length

McbspaRegs.SRGR2.bit.GSYNC = 0; //0 - No clock sync for CLKG
McbspaRegs.SRGR2.bit.FPER = 11; //11 - Frame-synch period, (11+1)*(1000/1200) = 10ms
McbspaRegs.SRGR2.bit.FSGM = 1; //1 - Frame-synch pulses from the sample rate generator

McbspaRegs.PCR.bit.SCLKME = 1;
McbspaRegs.SRGR2.bit.CLKSM = 0; //1-0 - SCLKME=1, CLKSM=0, Clock Signal on MCLKR pin

McbspaRegs.SRGR1.bit.CLKGDV = 0; //0 - Divide-down value for CLKG 1
delay_loop();
McbspaRegs.SRGR1.bit.FWID = 1; //1 - Frame-synchronization pulse width
delay_loop();

McbspaRegs.PCR.bit.FSXM = 1; //1 - FSX generated internally,
McbspaRegs.PCR.bit.FSRM = 0; //0 - FSR derived from an external source
McbspaRegs.PCR.bit.CLKXM = 1; //1 - CLKX generated internally
McbspaRegs.PCR.bit.CLKRM = 0; //0 - CLKR derived from an external source
McbspaRegs.PCR.bit.FSXP = 0; //0 - Transmit frame-synch pulses are active high
McbspaRegs.PCR.bit.FSRP = 0; //0 - Receive frame-synch pulses are active high
McbspaRegs.PCR.bit.CLKXP = 1; //1 - Transmit data is sampled on the Falling edge of CLKX
McbspaRegs.PCR.bit.CLKRP = 1; //1 - Receive data is sampled on the rising edge of MCLKR

McbspaRegs.SPCR2.bit.GRST = 1; //1 - Enable Sample rate generator
delay_loop(); // wait at least 2 CLKG clock cycles
McbspaRegs.SPCR2.bit.XRST = 1; //1 - Release TX from Reset
McbspaRegs.SPCR1.bit.RRST = 1; //1 - Release RX from Reset
McbspaRegs.SPCR2.bit.FRST = 1; //1 - Frame Sync Generator reset
}