如题,怎么计算在单端模式下,单个ADC采样率最大是3.5Msps,手册也没有提及到
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参考下工程师的回复:
To calculate the ADC sample rate, add the chosen ACQPS value in seconds with the tEOC (also in seconds) and then take the inverse of this number:
Sample rate = 1 / (ACQPS + tEOC)
ACQPS: Sample-and-hold time; minimum of 75 ns based on hardware, provided by the datasheet (8.10.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode))
tEOC: Time from the end of the sample-and-hold window until the nextADC conversion can begin; provided in SYSCLKs, with a minimum of 44 based on the device frequency and maximum ADC clock frequency (provided by the datasheet in section 8.10.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode))
Make sure the ACQPS and tEOC are in the same units before using them in the above equation (here I've assumed you were talking about 12-bit single-ended mode).
参考下工程师的回复:
This example only uses 1 ADC, which will have some delay because it's doing 1 conversion and then reading that result. The best way to try and achieve a higher sampling rate is using many SOCs (all if possible). You can trigger the first SOC however you want and then have each EOC trigger the next SOC so that you are getting continuous conversions. If you are having the ePWM trigger each conversion on 1 SOC, the throughput of the ADC will most likely be lower than the maximum possible.
Also, keep in mind that depending on how long the ISR is (this example seems okay, but a customer use-case may vary), the sampling rate may be affected as well as the accuracy of the result.