TMS320F28379D: 當Debug 模式正常運作, 切換到Release 模式, 重新送電卻無法動作, 要如何確認問題

我需要一些时间来看一下

附上CMD 資料, 不知是否有影響

#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000123, length = 0x0002DD
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
RAMD0 : origin = 0x00B000, length = 0x000800
RAMD1 : origin = 0x00B800, length = 0x000800

RAMLS0to5 : origin = 0x008000, length = 0x003000
RAMGS0to4 : origin = 0x00C000, length = 0x005000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7to8 : origin = 0x013000, length = 0x002000
RAMGS9 : origin = 0x015000, length = 0x001000

RAMGS10to15 : origin = 0x016000, length = 0x005FF8
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
RESET : origin = 0x3FFFC0, length = 0x000002
PAGE 1:
FPGA_RAM1_1 : origin = 0x00100000, length = 0x001000 /* FPGA RAM 1.1, Store SDO object values */
FPGA_RAM1_2 : origin = 0x00101000, length = 0x001000 /* FPGA RAM 1.2, Store SDO object ECC values */
FPGA_RAM2 : origin = 0x00102000, length = 0x001000 /* FPGA RAM 2, Store CiA402 object values */
FPGA_RAM3to4 : origin = 0x00104000, length = 0x002000 /* FPGA RAM 3&4, Store oscilloscope data */

CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400

CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800

CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}

SECTIONS
{
codestart : > BEGIN
.text : >> FLASHD | FLASHE | FLASHF
.cinit : > FLASHA
.switch : > RAMM0
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMM1

#if defined(__TI_EABI__)
.init_array : >> RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3, ALIGN(8)
.bss : > RAMLS0 | RAMLS1, ALIGN(4)
.bss:output : > RAMLS0 | RAMLS1
.init_array : > RAMM0
.const : > RAMLS0 | RAMLS1
.data : > RAMLS0 | RAMLS1
.sysmem : > RAMLS0 | RAMLS1
#else
.pinit : >> RAMGS0to4, ALIGN(4)
.ebss : > RAMGS7to8, ALIGN(4)
.econst : > RAMGS10to15
.esysmem : > RAMGS9
#endif
ramfuncs : LOAD = FLASHJ,
RUN = RAMLS0to5,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)

unsecure_ramfuncs : LOAD = FLASHC,
RUN = RAMGS6,
LOAD_START(_UnSecureRamfuncsLoadStart),
LOAD_END(_UnSecureRamfuncsLoadEnd),
RUN_START(_UnSecureRamfuncsRunStart),
RUN_SIZE(_UnSecureRamfuncsRunSize),
RUN_END(_UnSecureRamfuncsRunEnd),
PAGE = 0, ALIGN(4)
ramfuncs
{ -l F021_API_F2837xD_FPU32.lib}
LOAD = FLASHF,
RUN = RAMGS0to4,
LOAD_START(_Flash021_API_LoadStart),
LOAD_END(_Flash021_API_LoadEnd),
RUN_START(_Flash021_API_RunStart),
RUN_SIZE(_Flash021_API_RunSize),
RUN_END(_Flash021_API_RunEnd),
PAGE = 0, ALIGN(4)
/* The following section definition are for IQMATH */
IQmath : > RAMGS5, PAGE=0
IQmathTables : > RAMGS5, PAGE=0
IQmathTablesRam : > RAMGS5, PAGE=0
Auto_Tuning_Code : > FLASHH, PAGE = 0

Spec_Object : > FPGA_RAM1_1, PAGE = 1
Spec_Object_ECC : > FPGA_RAM1_2, PAGE = 1
CiA402Bkup_Object : > FPGA_RAM2, PAGE = 1
Oci_Scop_Buff_SEC : > FPGA_RAM3to4, PAGE = 1

DEF_SPEC_OBJ : > FLASHK, PAGE = 0
DEF_CIA402_OBJ : > FLASHL, PAGE = 0
ramgs0 : > RAMGS6, type=NOINIT
ramgs1 : > RAMGS9, type=NOINIT

MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT

/* CLA specific sections */
Cla1Prog : >> RAMLS0to5
ClaData : > RAMLS0to5
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, type=NOINIT
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, type=NOINIT

/* SFRA specific sections */
SFRA_F32_Data : > RAMGS6, ALIGN = 64
sfra_data : > RAMGS6

#ifdef CLA_C
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS2

.scratchpad : > RAMLS2
.bss_cla : > RAMLS2
.const_cla : > RAMLS2
#endif //CLA_C

.TI.ramfunc : >> RAMGS0to4
}

Jordan Chen 说：

當Debug 模式正常運作, 切換到Release 模式

方便描述下操作的步骤吗？

1. 使用 Blackhawk USB560 V2 System Trace 做為Debug 工具

2. 在DSP 內用GPIO 點亮一顆LED 燈

3. 當在Debug 模式下, 按Debug icon. 當完成Down Load 後

4. 按下Resume icon. 然後就看到LED 燈亮

5. 然後將 Blackhawk USB560 V2 System Trace 拔掉, 斷電重開, LED 燈卻不會亮

6. 如此判斷, 無法Reboot

7. 順便一提,  也將CMD 檔內

    BEGIN : origin = 0x000000, length = 0x000002

 改為BEGIN : origin = 0x080000, length = 0x000002

 但依舊無法點亮LED 燈

如何確認?

你有进行过相关的操作吗？

我僅知CMD檔設定為燒錄Flash, 就甚為它應該全部燒錄到Flash, 還是有其他設定需要操作

codestart : > BEGIN
.text : >> FLASHD | FLASHE | FLASHF
.cinit : > FLASHA
.switch : > RAMM0
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMM1

更换cmd后编译的时候有报错吗？