Other Parts Discussed in Thread: SYSCONFIG, C2000WARE
如题所示，我把例程SysConfig生成的CMD文件跟我的工程的CMD文件进行对比，我看不出区别在哪，可以帮我分析一下吗？上面的是我自己工程的CPU2CMD代码，下面的是例程ipc_ex4_msgqueue_sysconfig_c28x2SysConfig生成的CMD代码，可以帮我分析一下我的CMD文件缺少什么部分吗？辛苦了，这个问题我找了一个月了！
//
// Active linker CMD configuration selected by
// the CMD Tool global settings
//
#define CMD0
#ifdef CMD0
MEMORY
{
RAMM0_BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x0000A2, length = 0x00035E
RAMM1 : origin = 0x000400, length = 0x0003F8
CLATOCPU_MSGRAM : origin = 0x001480, length = 0x000080
CPUTOCLA_MSGRAM : origin = 0x001500, length = 0x000080
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMD0 : origin = 0x00B000, length = 0x000800
RAMD1 : origin = 0x00B800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000
RAMGS11 : origin = 0x017000, length = 0x001000
RAMGS12 : origin = 0x018000, length = 0x001000
RAMGS13 : origin = 0x019000, length = 0x001000
RAMGS14 : origin = 0x01A000, length = 0x001000
RAMGS15 : origin = 0x01B000, length = 0x000FF8
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
FLASHA : origin = 0x080000, length = 0x002000
FLASHB : origin = 0x082000, length = 0x002000
FLASHC : origin = 0x084000, length = 0x002000
FLASHD : origin = 0x086000, length = 0x002000
FLASHE : origin = 0x088000, length = 0x008000
FLASHF : origin = 0x090000, length = 0x008000
FLASHG : origin = 0x098000, length = 0x008000
FLASHH : origin = 0x0A0000, length = 0x008000
FLASHI : origin = 0x0A8000, length = 0x008000
FLASHJ : origin = 0x0B0000, length = 0x008000
FLASHK : origin = 0x0B8000, length = 0x002000
FLASHL : origin = 0x0BA000, length = 0x002000
FLASHM : origin = 0x0BC000, length = 0x002000
FLASHN : origin = 0x0BE000, length = 0x001FF0
RESET : origin = 0x3FFFC0, length = 0x000002
}
SECTIONS
{
//
// C28x Sections
//
.reset : > RESET, TYPE = DSECT /* not used, */
codestart : > 0x000000
.text : >> FLASHB | FLASHC | FLASHD | FLASHE,
ALIGN(8)
.TI.ramfunc : LOAD > FLASHD,
RUN > RAMLS0,
TABLE(BINIT),
ALIGN(8)
.binit : > FLASHA,
ALIGN(8)
.ovly : > FLASHA,
ALIGN(8)
.cinit : > FLASHA,
ALIGN(8)
.stack : > RAMM1
.init_array : > FLASHB,
ALIGN(8)
.bss : > RAMLS5
.const : > FLASHF,
ALIGN(8)
.data : > RAMLS5
.switch : > FLASHA,
ALIGN(8)
.sysmem : > RAMLS5
MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
}
#endif
/*
//===========================================================================
// End of file.
//===========================================================================
*/
MEMORY
{
PAGE 0 :
RAMM0 : origin = 0x000080, length = 0x000380
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMGS14 : origin = 0x01A000, length = 0x001000
RAMGS15 : origin = 0x01B000, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 20012000
GROUP { /* GROUP memory ranges for crc/checksum of entire flash */
#endif
#endif
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
FLASHN_DO_NOT_USE : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 20012000
} crc(_ccs_flash_checksum, algorithm=C28_CHECKSUM_16)
#endif
#endif
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x00007E /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS14 : origin = 0x01A000, length = 0x001000//user add
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB PAGE = 0, ALIGN(4)
.pinit : > FLASHB, PAGE = 0, ALIGN(4)
.text : > FLASHB PAGE = 0, ALIGN(4)
codestart : > BEGIN PAGE = 0, ALIGN(4)
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#else
ramfuncs : LOAD = FLASHD,
RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
#endif
/* Allocate uninitalized data sections: */
.stack : > RAMM1 PAGE = 1
.ebss : > RAMLS5 PAGE = 1
.esysmem : > RAMLS5 PAGE = 1
/* Initalized sections go in Flash */
.econst : > FLASHB PAGE = 0, ALIGN(4)
.switch : > FLASHB PAGE = 0, ALIGN(4)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
SHARERAMGS0 : > RAMGS0, PAGE = 1
SHARERAMGS1 : > RAMGS1, PAGE = 1
readData2 : > RAMGS14, PAGE = 1
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
/* crc/checksum section configured as COPY section to avoid including in executable */
.TI.memcrc : type = COPY
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
