MSP430G2231 USI 配置成IIC 后，当iic的clk source 小于1MHZ就量不到。

Salyer Yang

Other Parts Discussed in Thread: MSP430G2231

当我讲system clk 配置成1Mhz，iic的clk source为SMCLK 不进行分频的换，我在p1.6 上能够量到clk 为1Mhz，当我对SMCLK 进行分频后就不能量到clk 了。

请问这是什么原因？

clk 配置如下：

void clk_init ()
{
DCOCTL = 0;/*clean DCO register bit*/
BCSCTL1 =0 ;
DCOCTL = CALDCO_1MHZ;/*set DCO frequency as calibration 1MHZ 25°C*/
BCSCTL1 |= CALBC1_1MHZ; /*MSP430G2231 haven't XT2,with DCOCTL BIT 5 6 7 to set DCO CLK calibration 16MHZ at 25°C*/

BCSCTL2 |=(DIVM_0+SELM_0+DIVS_3);//这样配置量不到
//BCSCTL2 |=(DIVM_0+SELM_0+DIVS_0);//这样配置能够量到
BCSCTL2 &= ~SELS;
}

9 年多前

0 灰小子 9 年多前

Guru 67475 points

你的iic怎么配置的？

0 Salyer Yang 9 年多前回复灰小子

Prodigy 20 points

void I2C_init()
{
USICTL0 |= USISWRST;
USICTL0 |= (USIPE6+USIPE7); //USI SDO/SCL port enable USI function enabled

/*I2C mode enable and setting*/
USICTL1 |=USII2C; //I2C mode enable

/*master mode setup*/
USICTL0 |= USIMST; //Master mode

USICKCTL = (USIDIV_0+USISSEL_2+USICKPL);//BIT 2.3.4 set source is SMCLK;Clock divider select is 1M/8*1,SCL is 125kHZ //Clock polarity select Inactive state is high
USICTL1 &= ~USICKPH; //Clock phase select Data is changed on the first SCLK edge and captured on the following edge.
USICTL0 &= ~USILSB; //MSB first
USICNT &= ~USI16B; //8-bit shift register mode. Low byte register USISRL is used.

USICTL1 |= USIIE;//enable counter interrupt
USICTL1 &= ~(USISTTIE+USISTTIFG);//Interrupt on START condition disabled;No START condition received. No interrupt pending.

//USICNT |= USIIFGCC; //USIIFG is not cleared automatically
USICNT &= ~USIIFGCC;
//bring USI out of reset status
USICTL0 &= ~USISWRST;
}

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MSP430G2231 USI 配置成IIC 后，当iic的clk source 小于1MHZ就量不到。