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When LPMx.5 (LPM3.5 or LPM4.5) is entered, the voltage regulator of the Power Management Module (PMM) is disabled. All RAM and register contents are lost. Although the I/O register contents are lost, the I/O pin states are locked upon LPMx.5 entry. See the Digital I/O chapter for further details. Wakeup from LPM4.5 is possible via a power sequence, a RST event, or from specific I/O. Wakeup from LPM3.5 is possible via a power sequence, a RST event, RTC event, or from specific I/O
