MSP430F2419: 管脚配置异常

Ice丶Dragon

Prodigy 91 points

Part Number: MSP430F2419

图所示为项目中MSP430F4219的初始化配置（XT2=8MHz），其中注释部分（P6）在调试时异常。

现象：

1、该段代码注释后系统正常运行；加入该段代码，系统无法完成管脚初始化配置；

2、将未注释的代码下载到另一个项目的板子（XT2=6MHz）上，管脚能正常初始化配置。

请教下大家，出现这种问题的原因以及解决的办法。谢谢！

4 年多前

0 Susan Yang 4 年多前

TI__Guru**** 252096 points

q请问是否有直接测试TI例程？您现在测试的有问题的板子，P6的功能是什么？

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 *******************************************************************************
 * 
 *                       MSP430 CODE EXAMPLE DISCLAIMER
 *
 * MSP430 code examples are self-contained low-level programs that typically
 * demonstrate a single peripheral function or device feature in a highly
 * concise manner. For this the code may rely on the device's power-on default
 * register values and settings such as the clock configuration and care must
 * be taken when combining code from several examples to avoid potential side
 * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
 * for an API functional library-approach to peripheral configuration.
 *
 * --/COPYRIGHT--*/
//******************************************************************************
//  MSP430x26x Demo - Basic Clock, MCLK Configured to Operate from XT2 HF XTAL
//
//  Description: Proper selection of an external HF XTAL for MCLK is shown
//  using HF XT2 OSC. OFIFG is polled until the HF XTAL is stable; only then is 
//  MCLK sourced by XT2.  MCLK is buffered on P5.4 and MCLK/10 is on P1.1 driven 
//  by a software loop taking exactly 10 CPU cycles.
//  ACLK = MCLK = LFXT1 = HF XTAL, SMCLK = default DCO ~1.045MHz
//  //* XT2 HF XTAL NOT INSTALLED ON FET *//
//  //* Min Vcc required varies with MCLK frequency - refer to datasheet *//
//
//              MSP430F261x/241x
//             -----------------
//         /|\|              XIN|-
//          | |                 |
//          --|RST          XOUT|-
//            |                 |
//            |                 |
//            |            XT2IN|-
//            |                 | HF XTAL (400kHz - 16MHz)
//            |           XT2OUT|-
//            |                 |
//            |             P1.1|-->MCLK/10 = XT2 HFXTAL/10
//            |        P5.4/MCLK|-->MCLK = XT2 HFXTAL
//
//  B. Nisarga
//  Texas Instruments Inc.
//  September 2007
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.42A
//******************************************************************************
#include <msp430.h>

volatile unsigned int i;

int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT

  P5DIR |= 0x10;                            // P5.4= output direction
  P5SEL |= 0x10;                            // P5.4= MCLK option select
  P1DIR |= 0x02;                            // P1.1 = output direction

  BCSCTL1 &= ~XT2OFF;                       // Activate XT2 high freq xtal
  BCSCTL3 |= XT2S_2;                        // 3 � 16MHz crystal or resonator

  do
  {
    IFG1 &= ~OFIFG;                         // Clear OSCFault flag
    for (i = 0xFF; i > 0; i--);             // Time for flag to set
  }
  while (IFG1 & OFIFG);                     // OSCFault flag still set?

  BCSCTL2 |= SELM_2;                        // MCLK = XT2 HF XTAL (safe)

  for (;;)                                  // Infinite loop
  {
    P1OUT |= 0x02;                          // P1.1 = 1
    P1OUT &= ~0x02;                         // P1.1 = 0
  }
}