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MSP430F5308: 怎样实现将XT2BYPASS 输入的4MHz时钟作为FLL reference clock,并通过FLL设置 倍频至24MHz时钟,将其作为MCLK时钟源输出

Part Number: MSP430F5308

怎样实现通过XT2BYPASS 输入4MHz时钟源,并将其作为FLL reference clock,并通过FLL设置 倍频至24MHz时钟,将其作为MCLK时钟源输出?

不知道下面code为什么OFIFG一直处于被置位状态,且输出频率也远不是24MHz?该如何改正,能不能解释一下?能不能在不设置低功耗模式下实现功能?


#define M_LED3_Off() (P6DIR |= BIT1, P6OUT &= ~BIT1)
#define M_LED3_On() (P6DIR |= BIT1, P6OUT |= BIT1)

void SetVcoreUp (unsigned int level);

int main(void)
{
volatile unsigned int i;

WDTCTL = WDTPW|WDTHOLD; // Stop WDT

PMAPPWD = 0x02D52; // Enable Write-access to modify port mapping registers
P4MAP7 = PM_MCLK;
PMAPPWD = 0; // Disable Write-Access to modify port mapping registers
P4SEL |= BIT7;
P4DIR |= BIT7; // MCLK set out to pins

P5SEL |= BIT2; // Enable XT2IN.
UCSCTL3 |= SELREF_5; // Set DCO FLL reference = XT2CLK
UCSCTL6 = XT1OFF;
UCSCTL6 |= XT2BYPASS;
UCSCTL4 = SELA__DCOCLK | SELS__DCOCLK | SELM__DCOCLK;

  SetVcoreUp (0x01);

__bis_SR_register(SCG0); // Disable the FLL control loop

UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 | 5;

__bic_SR_register(SCG0); // Enable the FLL control loop

__delay_cycles(375000);

// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag


M_LED3_On();

}

void SetVcoreUp (unsigned int level)
{
// Open PMM registers for write
PMMCTL0_H = PMMPW_H;
// Set SVS/SVM high side new level
SVSMHCTL = SVSHE | SVSHRVL0 * level | SVMHE | SVSMHRRL0 * level;
// Set SVM low side to new level
SVSMLCTL = SVSLE | SVMLE | SVSMLRRL0 * level;
// Wait till SVM is settled
while ((PMMIFG & SVSMLDLYIFG) == 0);
// Clear already set flags
PMMIFG &= ~(SVMLVLRIFG | SVMLIFG);
// Set VCore to new level
PMMCTL0_L = PMMCOREV0 * level;
// Wait till new level reached
if ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0);
// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE | SVSLRVL0 * level | SVMLE | SVSMLRRL0 * level;
// Lock PMM registers for write access
PMMCTL0_H = 0x00;
}