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TI的老师们好：
如题目所示，为何RAIL2的VID管脚要和FPGA连起来呢？FPGA为何会对RCD9222的工作状态产生影响呢？还是说仅仅只是RFU，并不一定会使用
请参考下面的帖子。
https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/237122/problem-about-ucd9222-s-vid/831307
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/131297/tmdxevm6678l-smart-reflex-circuit
谢谢老师。
