int32_t Ipc_setCoreEventId(uint32_t selfId, Ipc_MbConfig* cfg, uint32_t intrCnt)
/* Allocate the last 5 interrupts for IPC. Note that the IR allocation is
* static so this needs to be carefully set. Currently first interrupt is
* used by UDMA and middle one's are used by other modules like CPSW9G so
* we are using last 5 as a safe option.
*/
There are two questions.
1. The above functions are the functions to get the interrupt configuration call. The content annotated in the function is the mailbox for IPC. Can only the last five interrupts be used? I understand that there are 12 HW mailboxes, each with four interrupts? Isn't there 48 interrupts in total?
2. By looking at the sdk-rtos-0800 code, I can see that there is a pair of vring between each pair of processors. Finally, the maibox distinguishes the sending or receiving direction of vring by sending 0 or 1.
Can there only be one pair of vring between a pair of processors?
Please help to answer, thank you.