AM5708: gpmc初始化

?? ?

Part Number: AM5708
Other Parts Discussed in Thread: SYSCONFIG

您好，AM5708不跑arm，在DSP下裸跑gpmc，gpmc初始化代码如下：

int GPMC_padConfig()
{
CSL_ipu_cm_core_aonRegs *ipu_cm_core_aonRegs = \
((CSL_ipu_cm_core_aonRegs *)CSL_DSP_IPU_CM_CORE_AON_REGS);
CSL_core_cm_coreRegs *core_cm_coreRegs = \
((CSL_core_cm_coreRegs *)CSL_DSP_CORE_CM_CORE_REGS);
CSL_control_core_pad_ioRegs *core_pad_ioRegs = \
((CSL_control_core_pad_ioRegs *)CSL_MPU_CORE_PAD_IO_REGISTERS_REGS);

core_cm_coreRegs->CM_L3MAIN1_L3_MAIN_1_CLKCTRL_REG = \
CM_L3MAIN1_GPMC_CLKCTRL_MODULEMODE_MASK;
//Enable GPMC clock
core_cm_coreRegs->CM_L3MAIN1_GPMC_CLKCTRL_REG = \
CM_L3MAIN1_GPMC_CLKCTRL_MODULEMODE_AUTO;
/*GPMC Data lines AD0-AD15*/
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD0,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD1,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD2,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD3,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD4,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD5,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD6,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD7,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD8,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD9,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD10,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD11,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD12,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD13,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD14,0x00050000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_AD15,0x00050000);
/*GPMC Add lines A0-A27*/
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A0,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A1,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A2,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A3,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A4,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A5,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A6,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A7,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A8,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A9,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A10,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A11,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A12,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A13,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A14,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A15,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A16,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A17,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A18,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A19,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A20,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A21,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A22,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A23,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A24,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A25,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A26,0x00040000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_A27,0x00040000);

HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_CLK,0x00060000);

/*GPMC chip select*/
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_CS0,0x00020000);
/*GPMC control lines*/
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_ADVN_ALE,0x00060000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_OEN_REN,0x00020000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_WEN,0x00020000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_BEN0,0x00070000);
HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_GPMC_WAIT0,0x000F0000);

return 0;
}

GPMC_Config_t GPMC_ConfigNorDefault = {
/* SysConfig - ROM Code defaults */
0x0, /*0x0008,*/
/* IRQEnable - ROM Code defaults */
0x0000,
/* TimeOutControl - ROM Code defaults */
0xf01f0000,
/* Config - ROM Code defaults */
0x000a0000,
{
0x00001010,//0x00001010
0x001e1e01,
0x00090907,
0xf071d0b,
0x001c1f1f,
0x8f070080,
0x00000f48,//0x00000f48
},
};

void GPMC_Init(GPMC_Config_t *cfg, uint8_t cs)
{
uint8_t i;
xdc_Int ret = !Resource_S_SUCCESS;
xdc_UInt32 *va = (UInt32*)0x50000000;
ret = Resource_physToVirt(0x50000000, (UInt32 *)&va);
//if (ret == Resource_S_SUCCESS) {
/* program global GPMC regs */
GPMC_Write(GPMC_SYSCONFIG_OFF, cfg->SysConfig);
GPMC_Write(GPMC_IRQENABLE_OFF, cfg->IrqEnable);
GPMC_Write(GPMC_TIMEOUTCTRL_OFF, cfg->TimeOutControl);
GPMC_Write(GPMC_CONFIG_OFF, cfg->Config);
*(UInt32*)0x50000040 = cfg->TimeOutControl;
*(UInt32*)0x50000050 = cfg->Config;
//}

/* program GPMC CS specific registers */
/* disable cs */
GPMC_CSWrite(cs, GPMC_CONFIG7_OFF, 0x00000000);
DEVICE_Delay(MAX_DELAY);

/* program new set of config values (1 to 7) */
for (i = 0; i < GPMC_MAX_CS; i++) {
GPMC_CSWrite(cs, (i * 4), cfg->ChipSelectConfig[i]);
}

/* enable cs */
GPMC_CSWrite(cs, GPMC_CONFIG7_OFF, (cfg->ChipSelectConfig[6] | 0x40));
DEVICE_Delay(MAX_DELAY);
}

/* Select the chip-select base address, chip addr needs to be given */
GPMCBaseAddrSet(CSL_MPU_GPMC_CONF_REGS_REGS, GPMC_CHIP_SELECT_0, 0x00000008);

/* Select the chip-select mask address */
GPMCMaskAddrSet(CSL_MPU_GPMC_CONF_REGS_REGS, GPMC_CHIP_SELECT_0, GPMC_CS_SIZE_64MB);

//读写地址

ptr_ad = (volatile UInt16*)(0x08000000 & 0x0C000000);
for(i=0;i<100;i++)
{
//*(ptr_ad + i) = i;
*(ptr_ad + 4 * i) = 0x5a5a+ 10 * i;
//*((UInt32*)(0x010000A0 + (10*i))) = i;
//((uint16_t *)g_device_vir_addr)[i] = i;
}
for(i=0;i<100;i++)
{
//test[i] = *(ptr_ad + i);
test[i] = *(ptr_ad + 4 * i);
//test[i] = ((uint16_t *)g_device_vir_addr)[0];
}

读写0x08000000 地址，片选信号及读写信号全没有，请问初始化还需要哪些寄存器？

9 个月前