TDA4VM: DSI Display exception with 1280*800

We have modified the timing and it can be displayed initially. How do I need to change this color mode? Can anyone reply? Thanks

Regards,

Barry

Hello，

It looks like you have provided a list of changes made to your software, and you are seeking help to understand the situation. It appears that you have made changes related to the display and camera interfaces in your software stack for the TDA4VM-DSI, MAX96789, MAX96752, and LVDS to LCD data flow.

Here's a high-level overview of the changes you've made based on the provided information:

1. Changes in app_common.h, main.c, app_display_module.h, and app_display_module.c: These changes likely involve modifications to the application's common header file, main application file, and display module header and source files. These changes may involve configuring the display and camera interfaces, as well as integrating the TIDL (Texas Instruments Deep Learning) application with the display module.

2. Modification in app_cfg_mcu2_0.h: This change involves modifying the configuration for the MCU2_0 subsystem, likely related to the display and camera interfaces.

3. Update in app_init.c, app_dctrl.c, and app_dss_defaults.c: These changes are likely related to initializing and configuring the display subsystem (DSS) and display controller (DCTRL) for the TDA4VM-DSI and LVDS interfaces.

Based on the provided information, it seems that you have made several changes to integrate the TDA4VM-DSI, MAX96789, MAX96752, and LVDS to LCD data flow with the TIDL application and the display subsystem.

Regards，

Gary

Hello，

To change the color mode of the display, you will typically need to modify the configuration of the display subsystem in your software. Here are the general steps you can follow to change the color mode:

1. Locate the Display Configuration: Identify the configuration files or source code related to the display subsystem in your software. This may include files that define the display timing, format, and color mode.

2. Update Color Mode Settings: Look for settings related to the color mode in the display configuration. This may include parameters such as color depth, pixel format, gamma correction, or color space conversion.

3. Modify Color Mode Parameters: Depending on the specific requirements of your display, you may need to adjust the color mode parameters to match the desired color mode. This could involve changing the pixel format from RGB to YUV, adjusting the color depth (e.g., 24-bit color to 16-bit color), or configuring specific color space conversion settings.

4. Rebuild and Deploy: After making the necessary changes to the color mode settings, rebuild the software and deploy it to the target hardware to observe the updated color mode on the display.

Regards，

Gary

Hi Experts,

Can you tell me the specific location of the code to be modified? How should we modify the color mode code in TIDL? Please help us solve this abnormal display problem, thank you

What we see when we run tidl is this:

Regards,

Barry

Hello，

To modify the color mode code in TIDL, you will need to locate the specific part of the code that handles color mode settings. This could be in the configuration file, a separate color mode module, or within the main TIDL codebase.

Once you have located the code related to color mode, you can modify it according to your requirements. This may involve changing color space conversions, adjusting color balance, or implementing specific color mode algorithms.

To solve the abnormal display problem, you may also need to consider other factors such as input data format, display settings, and any additional image processing steps within your TIDL pipeline.

Regards，

Gary

Are you a robot? Could you please help me access your technicians? We need to know the specific modification points,please help us.

Regards,

Barry

The engineer is being consulted, please be patient

Hi Experts,

We are looking forward to your reply, please help us, thank you

Regards,

Barry

Hello，

The following is the engineer's reply:

Sorry what's the exception that you are seeing? 

Also are the pixel clock and lane speed setup correctly ? It shows only 7.5fps with display node taking around 58ms to display a frame.. 

Hi Experts,

thanks for your response

1. The abnormal problem is that the TIDL image output on the screen is unclear. The image I expect to see should be consistent with the output of run_app_tidl.sh.

2. Why is my output only 7.5FPS? How should I adjust the TIDL_demo code to output 60FPS?

please tell me thank you ,Looking forward to your reply

Regards,

Barry

HI TI,

When I execute ./run_app_tidl.sh on the EVM, the output frame rate when the DP can be displayed normally is 10FPS. I see that the pixel clock in the code is set to 60FPS.The following is my DP output log on the EVM,Can you help me understand this problem?

How should I adjust TIDL to output 60FPS?

root@j7-evm:/opt/vision_apps# source ./vision_apps_init.sh 
root@j7-evm:/opt/vision_apps# [MCU2_0]   3000.433226 s: CIO: Init ... Done !!!
[MCU2_0]   3000.433294 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0]   3000.433334 s: CPU is running FreeRTOS
[MCU2_0]   3000.433359 s: APP: Init ... !!!
[MCU2_0]   3000.433383 s: SCICLIENT: Init ... !!!
[MCU2_0]   3000.433684 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_0]   3000.433733 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_0]   3000.433765 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0]   3000.433800 s: SCICLIENT: Init ... Done !!!
[MCU2_0]   3000.433827 s: UDMA: Init ... !!!
[MCU2_0]   3000.435111 s: UDMA: Init ... Done !!!
[MCU2_0]   3000.435175 s: MEM: Init ... !!!
[MCU2_0]   3000.435218 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d9000000 of size 1677721!
[MCU2_0]   3000.435290 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!!
[MCU2_0]   3000.435350 s: MEM: Init ... Done !!!
[MCU2_0]   3000.435376 s: IPC: Init ... !!!
[MCU2_0]   3000.435434 s: IPC: 6 CPUs participating in IPC !!!
[MCU2_0]   3000.435484 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]   3012.071190 s: IPC: HLOS is ready !!!
[MCU2_0]   3012.086599 s: IPC: Init ... Done !!!
[MCU2_0]   3012.086663 s: APP: Syncing with 5 CPUs ... !!!
[MCU2_0]   3012.281753 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_0]   3012.281974 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]   3012.283542 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]   3012.283605 s: ETHFW: Init ... !!!
[MCU2_0]   3012.288399 s: Warning: Using 6 MAC address(es) from static pool
[MCU2_0]   3012.288611 s: ETHFW: Shared multicasts (software fanout):
[MCU2_0]   3012.288670 s: ETHFW: Reserved multicasts:
[MCU2_0]   3012.288705 s:   01:80:c2:00:00:0e
[MCU2_0]   3012.288756 s:   01:1b:19:00:00:00
[MCU2_0]   3012.289089 s: EnetMcm: CPSW_9G on MAIN NAVSS
[MCU2_0]   3012.298576 s: Mdio_open: MDIO manual mode enabled
[MCU2_0]   3012.302606 s: PHY 16 is alive
[MCU2_0]   3012.302758 s: PHY 17 is alive
[MCU2_0]   3012.302867 s: PHY 18 is alive
[MCU2_0]   3012.302983 s: PHY 19 is alive
[MCU2_0]   3012.306215 s: 
[MCU2_0] ETHFW Version   : 0.02.00
[MCU2_0]   3012.306294 s: ETHFW Build Date: Nov 27, 2023
[MCU2_0]   3012.306328 s: ETHFW Build Time: 15:11:31
[MCU2_0]   3012.306355 s: ETHFW Commit SHA: d19b4855
[MCU2_0]   3012.306427 s: ETHFW: Init ... DONE !!!
[MCU2_0]   3012.306462 s: ETHFW: Remove server Init ... !!!
[MCU2_0]   3012.306642 s: CpswProxyServer: Virtual port configuration:
[MCU2_0]   3012.306703 s:   mpu_1_0 <-> Switch port 0: mpu_1_0_ethswitch-device-0
[MCU2_0]   3012.306748 s:   mcu_2_1 <-> Switch port 1: mcu_2_1_ethswitch-device-1
[MCU2_0]   3012.306790 s:   mpu_1_0 <-> MAC port 1: mpu_1_0_ethmac-device-1
[MCU2_0]   3012.306830 s:   mcu_2_1 <-> MAC port 4: mcu_2_1_ethmac-device-4
[MCU2_0]   3012.307863 s: CpswProxyServer: initialization completed (core: mcu2_0)
[MCU2_0]   3012.307929 s: ETHFW: Remove server Init ... DONE !!!
[MCU2_0]   3012.309094 s: Starting lwIP, local interface IP is dhcp-enabled
[MCU2_0]   3012.316967 s: Host MAC address: 70:ff:76:1d:92:c3
[MCU2_0]   3012.321211 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
[MCU2_0]   3012.321308 s: Added interface 'ti1', IP is 0.0.0.0
[MCU2_0]   3012.357983 s: FVID2: Init ... !!!
[MCU2_0]   3012.358091 s: FVID2: Init ... Done !!!
[MCU2_0]   3012.358145 s: DSS: Init ... !!!
[MCU2_0]   3012.358175 s: DSS: Display type is eDP !!!
[MCU2_0]   3012.358204 s: DSS: M2M Path is enabled !!!
[MCU2_0]   3012.358231 s: DSS: SoC init ... !!!
[MCU2_0]   3012.358255 s: SCICLIENT: Sciclient_pmSetModuleState module=152 state=2
[MCU2_0]   3012.358489 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.358532 s: SCICLIENT: Sciclient_pmSetModuleState module=297 state=2
[MCU2_0]   3012.358729 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.358763 s: SCICLIENT: Sciclient_pmSetModuleState module=151 state=2
[MCU2_0]   3012.358912 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.358946 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=9 parent=11

[MCU2_0]   3012.359189 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]   3012.359233 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=13 parent=18
[MCU2_0]   3012.359350 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]   3012.359388 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=152 clk=1 parent=2
[MCU2_0]   3012.359485 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0]   3012.359519 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=152 clk=1 freq=148500000
[MCU2_0]   3012.360733 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]   3012.360787 s: SCICLIENT: Sciclient_pmModuleClkRequest module=152 clk=1 state=2 flag=0
[MCU2_0]   3012.360953 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0]   3012.361070 s: DSS: SoC init ... Done !!!
[MCU2_0]   3012.361103 s: DSS: Board init ... !!!
[MCU2_0]   3012.361127 s: DSS: Board init ... Done !!!
[MCU2_0]   3012.424451 s: DSS: Init ... Done !!!
[MCU2_0]   3012.424519 s: VHWA: VPAC Init ... !!!
[MCU2_0]   3012.424549 s: SCICLIENT: Sciclient_pmSetModuleState module=290 state=2
[MCU2_0]   3012.424748 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.424787 s: VHWA: LDC Init ... !!!
[MCU2_0]   3012.428663 s: VHWA: LDC Init ... Done !!!
[MCU2_0]   3012.428728 s: VHWA: MSC Init ... !!!
[MCU2_0]   3012.441079 s: VHWA: MSC Init ... Done !!!
[MCU2_0]   3012.441145 s: VHWA: NF Init ... !!!
[MCU2_0]   3012.443111 s: VHWA: NF Init ... Done !!!
[MCU2_0]   3012.443177 s: VHWA: VISS Init ... !!!
[MCU2_0]   3012.454397 s: VHWA: VISS Init ... Done !!!
[MCU2_0]   3012.454464 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]   3012.454510 s:  VX_ZONE_INIT:Enabled
[MCU2_0]   3012.454539 s:  VX_ZONE_ERROR:Enabled
[MCU2_0]   3012.454565 s:  VX_ZONE_WARNING:Enabled
[MCU2_0]   3012.456187 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-0 
[MCU2_0]   3012.456450 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_NF 
[MCU2_0]   3012.456683 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_LDC1 
[MCU2_0]   3012.457129 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC1 
[MCU2_0]   3012.457404 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_MSC2 
[MCU2_0]   3012.457683 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target VPAC_VISS1 
[MCU2_0]   3012.457938 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE1 
[MCU2_0]   3012.458326 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE2 
[MCU2_0]   3012.458603 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY1 
[MCU2_0]   3012.458875 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DISPLAY2 
[MCU2_0]   3012.459246 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CSITX 
[MCU2_0]   3012.459542 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE3 
[MCU2_0]   3012.459814 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE4 
[MCU2_0]   3012.460190 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE5 
[MCU2_0]   3012.460502 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE6 
[MCU2_0]   3012.460781 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE7 
[MCU2_0]   3012.461179 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target CAPTURE8 
[MCU2_0]   3012.461453 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M1 
[MCU2_0]   3012.461698 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M2 
[MCU2_0]   3012.461931 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M3 
[MCU2_0]   3012.462345 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DSS_M2M4 
[MCU2_0]   3012.462413 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_0]   3012.462451 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]   3012.474073 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]   3012.484072 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]   3012.484135 s: CSI2RX: Init ... !!!
[MCU2_0]   3012.484162 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]   3012.484301 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.484344 s: SCICLIENT: Sciclient_pmSetModuleState module=26 state=2
[MCU2_0]   3012.484509 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.484542 s: SCICLIENT: Sciclient_pmSetModuleState module=27 state=2
[MCU2_0]   3012.484678 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.484712 s: SCICLIENT: Sciclient_pmSetModuleState module=147 state=2
[MCU2_0]   3012.484808 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.484840 s: SCICLIENT: Sciclient_pmSetModuleState module=148 state=2
[MCU2_0]   3012.484929 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.485266 s: CSI2RX: Init ... Done !!!
[MCU2_0]   3012.485318 s: CSI2TX: Init ... !!!
[MCU2_0]   3012.485343 s: SCICLIENT: Sciclient_pmSetModuleState module=25 state=2
[MCU2_0]   3012.485452 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.485492 s: SCICLIENT: Sciclient_pmSetModuleState module=28 state=2
[MCU2_0]   3012.485645 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.485681 s: SCICLIENT: Sciclient_pmSetModuleState module=296 state=2
[MCU2_0]   3012.485809 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]   3012.485891 s: CSI2TX: Init ... Done !!!
[MCU2_0]   3012.485926 s: ISS: Init ... !!!
[MCU2_0]   3012.486079 s: Found sensor IMX390-UB953_D3 at location 0 
[MCU2_0]   3012.486146 s: Found sensor AR0233-UB953_MARS at location 1 
[MCU2_0]   3012.486187 s: Found sensor AR0820-UB953_LI at location 2 
[MCU2_0]   3012.486224 s: Found sensor UB9xxx_RAW12_TESTPATTERN at location 3 
[MCU2_0]   3012.486262 s: Found sensor UB96x_UYVY_TESTPATTERN at location 4 
[MCU2_0]   3012.486301 s: Found sensor GW_AR0233_UYVY at location 5 
[MCU2_0]   3012.486335 s: IssSensor_Init ... Done !!!
[MCU2_0]   3012.486431 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]   3012.486470 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]   3012.486544 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]   3012.486578 s: UDMA Copy: Init ... !!!
[MCU2_0]   3012.488596 s: UDMA Copy: Init ... Done !!!
[MCU2_0]   3012.488707 s: APP: Init ... Done !!!
[MCU2_0]   3012.488747 s: APP: Run ... !!!
[MCU2_0]   3012.488773 s: IPC: Starting echo test ...
[MCU2_0]   3012.491748 s: APP: Run ... Done !!!
[MCU2_0]   3012.493207 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[.] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]   3012.493728 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_0]   3012.493846 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_0]   3012.493940 s: IPC: Echo status: mpu1_0[x] mcu2_0[s] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_0]   3012.601465 s: Function:CpswProxyServer_attachExtHandlerCb,HostId:0,CpswType:6
[MCU2_0]   3014.956721 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38acb1
[MCU2_0]   3014.960109 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38e
[MCU2_0]   3014.960414 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38e
[MCU2_0]   3014.968287 s: Function:CpswProxyServer_registerMacHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38acb0
[MCU2_0]   3014.971460 s: Cpsw_ioctlInternal: CPSW: Registered MAC address. ALE entry:11, Policer Entry:2
[MCU2_0]   3014.971826 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38ac0
[MCU2_0]   3014.975383 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38ac0
[MCU2_0]   3014.985891 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38e
[MCU2_0]   3014.987613 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38ac0
[MCU2_0]   3015.018586 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38e
[MCU2_0]   3015.041578 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38ac0
[MCU2_0]   3015.045096 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38ac0
[MCU2_0]   3015.048547 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38ac0
[MCU2_0]   3015.048695 s: CpswProxyServer_isRsvdMcast: Reserved mcast cannot be added to filter
[MCU2_0]   3015.242711 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38e
[MCU2_0]   3015.242892 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38ac0
[MCU2_0]   3016.594264 s: Function:CpswProxyServer_filterAddMacHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38ac0
[MCU2_0]   3017.039914 s: Function:CpswProxyServer_setPromiscModeHandlerCb,HostId:0,Handle:a3ac6414,CoreKey:38e
[MCU2_1]   3000.376528 s: CIO: Init ... Done !!!
[MCU2_1]   3000.376600 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1]   3000.376642 s: CPU is running FreeRTOS
[MCU2_1]   3000.376668 s: APP: Init ... !!!
[MCU2_1]   3000.376691 s: SCICLIENT: Init ... !!!
[MCU2_1]   3000.376941 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[MCU2_1]   3000.376991 s: SCICLIENT: DMSC FW revision 0x8  
[MCU2_1]   3000.377027 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1]   3000.377080 s: SCICLIENT: Init ... Done !!!
[MCU2_1]   3000.377109 s: UDMA: Init ... !!!
[MCU2_1]   3000.378519 s: UDMA: Init ... Done !!!
[MCU2_1]   3000.378585 s: MEM: Init ... !!!
[MCU2_1]   3000.378630 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ da000000 of size 1677721!
[MCU2_1]   3000.378709 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 3640000 of size 262144 bytes !!!
[MCU2_1]   3000.378773 s: MEM: Init ... Done !!!
[MCU2_1]   3000.378800 s: IPC: Init ... !!!
[MCU2_1]   3000.378861 s: IPC: 6 CPUs participating in IPC !!!
[MCU2_1]   3000.378911 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1]   3012.266422 s: IPC: HLOS is ready !!!
[MCU2_1]   3012.281632 s: IPC: Init ... Done !!!
[MCU2_1]   3012.281701 s: APP: Syncing with 5 CPUs ... !!!
[MCU2_1]   3012.281751 s: APP: Syncing with 5 CPUs ... Done !!!
[MCU2_1]   3012.281787 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1]   3012.283555 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1]   3012.283621 s: FVID2: Init ... !!!
[MCU2_1]   3012.283690 s: FVID2: Init ... Done !!!
[MCU2_1]   3012.283724 s: VHWA: DMPAC: Init ... !!!
[MCU2_1]   3012.283749 s: SCICLIENT: Sciclient_pmSetModuleState module=48 state=2
[MCU2_1]   3012.284257 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]   3012.284304 s: SCICLIENT: Sciclient_pmSetModuleState module=305 state=2
[MCU2_1]   3012.284747 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1]   3012.284782 s: VHWA: DOF Init ... !!!
[MCU2_1]   3012.293522 s: VHWA: DOF Init ... Done !!!
[MCU2_1]   3012.293591 s: VHWA: SDE Init ... !!!
[MCU2_1]   3012.296318 s: VHWA: SDE Init ... Done !!!
[MCU2_1]   3012.296384 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1]   3012.296433 s:  VX_ZONE_INIT:Enabled
[MCU2_1]   3012.296466 s:  VX_ZONE_ERROR:Enabled
[MCU2_1]   3012.296491 s:  VX_ZONE_WARNING:Enabled
[MCU2_1]   3012.297900 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-1 
[MCU2_1]   3012.298153 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_SDE 
[MCU2_1]   3012.298381 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_DOF 
[MCU2_1]   3012.298439 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_1]   3012.298475 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1]   3012.298758 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1]   3012.298801 s: UDMA Copy: Init ... !!!
[MCU2_1]   3012.301147 s: UDMA Copy: Init ... Done !!!
[MCU2_1]   3012.301220 s: APP: Init ... Done !!!
[MCU2_1]   3012.301252 s: APP: Run ... !!!
[MCU2_1]   3012.301280 s: IPC: Starting echo test ...
[MCU2_1]   3012.303830 s: APP: Run ... Done !!!
[MCU2_1]   3012.305015 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[.] C7X_1[.] 
[MCU2_1]   3012.305146 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[.] 
[MCU2_1]   3012.305239 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[MCU2_1]   3012.493721 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[s] C66X_1[P] C66X_2[P] C7X_1[P] 
[C6x_1 ]   3000.431715 s: CIO: Init ... Done !!!
[C6x_1 ]   3000.431740 s: ### CPU Frequency = 1350000000 Hz
[C6x_1 ]   3000.431750 s: CPU is running FreeRTOS
[C6x_1 ]   3000.431758 s: APP: Init ... !!!
[C6x_1 ]   3000.431766 s: SCICLIENT: Init ... !!!
[C6x_1 ]   3000.431965 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_1 ]   3000.431978 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_1 ]   3000.431988 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_1 ]   3000.431998 s: SCICLIENT: Init ... Done !!!
[C6x_1 ]   3000.432008 s: UDMA: Init ... !!!
[C6x_1 ]   3000.433527 s: UDMA: Init ... Done !!!
[C6x_1 ]   3000.433546 s: MEM: Init ... !!!
[C6x_1 ]   3000.433559 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ dc000000 of size 1677721!
[C6x_1 ]   3000.433576 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_1 ]   3000.433592 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ dd000000 of size 50331!
[C6x_1 ]   3000.433608 s: MEM: Init ... Done !!!
[C6x_1 ]   3000.433617 s: IPC: Init ... !!!
[C6x_1 ]   3000.433638 s: IPC: 6 CPUs participating in IPC !!!
[C6x_1 ]   3000.433652 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_1 ]   3011.704187 s: IPC: HLOS is ready !!!
[C6x_1 ]   3011.708000 s: IPC: Init ... Done !!!
[C6x_1 ]   3011.708028 s: APP: Syncing with 5 CPUs ... !!!
[C6x_1 ]   3012.281751 s: APP: Syncing with 5 CPUs ... Done !!!
[C6x_1 ]   3012.281764 s: REMOTE_SERVICE: Init ... !!!
[C6x_1 ]   3012.282452 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_1 ]   3012.282495 s:  VX_ZONE_INIT:Enabled
[C6x_1 ]   3012.282506 s:  VX_ZONE_ERROR:Enabled
[C6x_1 ]   3012.282516 s:  VX_ZONE_WARNING:Enabled
[C6x_1 ]   3012.283306 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_1 ]   3012.283320 s: APP: OpenVX Target kernel init ... !!!
[C6x_1 ]   3012.283583 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_1 ]   3012.283599 s: UDMA Copy: Init ... !!!
[C6x_1 ]   3012.287349 s: UDMA Copy: Init ... Done !!!
[C6x_1 ]   3012.287369 s: APP: Init ... Done !!!
[C6x_1 ]   3012.287378 s: APP: Run ... !!!
[C6x_1 ]   3012.287386 s: IPC: Starting echo test ...
[C6x_1 ]   3012.288418 s: APP: Run ... Done !!!
[C6x_1 ]   3012.288729 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[x] C7X_1[P] 
[C6x_1 ]   3012.289251 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]   3012.304369 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_1 ]   3012.493576 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[s] C66X_2[P] C7X_1[P] 
[C6x_2 ]   3000.513829 s: CIO: Init ... Done !!!
[C6x_2 ]   3000.513855 s: ### CPU Frequency = 1350000000 Hz
[C6x_2 ]   3000.513866 s: CPU is running FreeRTOS
[C6x_2 ]   3000.513874 s: APP: Init ... !!!
[C6x_2 ]   3000.513882 s: SCICLIENT: Init ... !!!
[C6x_2 ]   3000.514080 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C6x_2 ]   3000.514092 s: SCICLIENT: DMSC FW revision 0x8  
[C6x_2 ]   3000.514102 s: SCICLIENT: DMSC FW ABI revision 3.1
[C6x_2 ]   3000.514113 s: SCICLIENT: Init ... Done !!!
[C6x_2 ]   3000.514123 s: UDMA: Init ... !!!
[C6x_2 ]   3000.515654 s: UDMA: Init ... Done !!!
[C6x_2 ]   3000.515673 s: MEM: Init ... !!!
[C6x_2 ]   3000.515687 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ e0000000 of size 1677721!
[C6x_2 ]   3000.515705 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 800000 of size 229376 bytes !!!
[C6x_2 ]   3000.515721 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ e1000000 of size 50331!
[C6x_2 ]   3000.515737 s: MEM: Init ... Done !!!
[C6x_2 ]   3000.515746 s: IPC: Init ... !!!
[C6x_2 ]   3000.515768 s: IPC: 6 CPUs participating in IPC !!!
[C6x_2 ]   3000.515782 s: IPC: Waiting for HLOS to be ready ... !!!
[C6x_2 ]   3011.971000 s: IPC: HLOS is ready !!!
[C6x_2 ]   3011.974749 s: IPC: Init ... Done !!!
[C6x_2 ]   3011.974775 s: APP: Syncing with 5 CPUs ... !!!
[C6x_2 ]   3012.281752 s: APP: Syncing with 5 CPUs ... Done !!!
[C6x_2 ]   3012.281764 s: REMOTE_SERVICE: Init ... !!!
[C6x_2 ]   3012.282468 s: REMOTE_SERVICE: Init ... Done !!!
[C6x_2 ]   3012.282502 s:  VX_ZONE_INIT:Enabled
[C6x_2 ]   3012.282513 s:  VX_ZONE_ERROR:Enabled
[C6x_2 ]   3012.282522 s:  VX_ZONE_WARNING:Enabled
[C6x_2 ]   3012.283317 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C6x_2 ]   3012.283331 s: APP: OpenVX Target kernel init ... !!!
[C6x_2 ]   3012.283587 s: APP: OpenVX Target kernel init ... Done !!!
[C6x_2 ]   3012.283609 s: UDMA Copy: Init ... !!!
[C6x_2 ]   3012.287723 s: UDMA Copy: Init ... Done !!!
[C6x_2 ]   3012.287746 s: APP: Init ... Done !!!
[C6x_2 ]   3012.287757 s: APP: Run ... !!!
[C6x_2 ]   3012.287765 s: IPC: Starting echo test ...
[C6x_2 ]   3012.288887 s: APP: Run ... Done !!!
[C6x_2 ]   3012.289195 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[.] 
[C6x_2 ]   3012.289260 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]   3012.304411 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C6x_2 ]   3012.493617 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[s] C7X_1[P] 
[C7x_1 ]   3000.737380 s: CIO: Init ... Done !!!
[C7x_1 ]   3000.737395 s: ### CPU Frequency = 1000000000 Hz
[C7x_1 ]   3000.737406 s: CPU is running FreeRTOS
[C7x_1 ]   3000.737415 s: APP: Init ... !!!
[C7x_1 ]   3000.737423 s: SCICLIENT: Init ... !!!
[C7x_1 ]   3000.737631 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
[C7x_1 ]   3000.737646 s: SCICLIENT: DMSC FW revision 0x8  
[C7x_1 ]   3000.737656 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ]   3000.737667 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]   3000.737677 s: UDMA: Init ... !!!
[C7x_1 ]   3000.738799 s: UDMA: Init ... Done !!!
[C7x_1 ]   3000.738812 s: MEM: Init ... !!!
[C7x_1 ]   3000.738824 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 117000000 of size 268435!
[C7x_1 ]   3000.738844 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 8159232 bytes !
[C7x_1 ]   3000.738862 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 458752 bytes !!
[C7x_1 ]   3000.738880 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ]   3000.738897 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ 100000000 of size 3858!
[C7x_1 ]   3000.738915 s: MEM: Init ... Done !!!
[C7x_1 ]   3000.738924 s: IPC: Init ... !!!
[C7x_1 ]   3000.738938 s: IPC: 6 CPUs participating in IPC !!!
[C7x_1 ]   3000.738952 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]   3012.202747 s: IPC: HLOS is ready !!!
[C7x_1 ]   3012.204786 s: IPC: Init ... Done !!!
[C7x_1 ]   3012.204801 s: APP: Syncing with 5 CPUs ... !!!
[C7x_1 ]   3012.281752 s: APP: Syncing with 5 CPUs ... Done !!!
[C7x_1 ]   3012.281768 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]   3012.281923 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]   3012.281946 s:  VX_ZONE_INIT:Enabled
[C7x_1 ]   3012.281957 s:  VX_ZONE_ERROR:Enabled
[C7x_1 ]   3012.281967 s:  VX_ZONE_WARNING:Enabled
[C7x_1 ]   3012.282137 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1 
[C7x_1 ]   3012.282242 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2 
[C7x_1 ]   3012.282347 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3 
[C7x_1 ]   3012.282415 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4 
[C7x_1 ]   3012.282481 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5 
[C7x_1 ]   3012.282557 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6 
[C7x_1 ]   3012.282671 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7 
[C7x_1 ]   3012.282739 s:  VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8 
[C7x_1 ]   3012.282761 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_1 ]   3012.282773 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]   3012.282912 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]   3012.282927 s: APP: Init ... Done !!!
[C7x_1 ]   3012.282936 s: APP: Run ... !!!
[C7x_1 ]   3012.282945 s: IPC: Starting echo test ...
[C7x_1 ]   3012.283098 s: APP: Run ... Done !!!
[C7x_1 ]   3012.288735 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[x] C7X_1[s] 
[C7x_1 ]   3012.289266 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]   3012.304439 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
[C7x_1 ]   3012.493654 s: IPC: Echo status: mpu1_0[x] mcu2_0[P] mcu2_1[P] C66X_1[P] C66X_2[P] C7X_1[s] 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# 
root@j7-evm:/opt/vision_apps# ./run_app_tidl.sh
APP: Init ... !!!
MEM: Init ... !!!
MEM: Initialized DMA HEAP (fd=4) !!!
MEM: Init ... Done !!!
IPC: Init ... !!!
IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
  3054.002114 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
  3054.007931 s:  VX_ZONE_INIT:Enabled
  3054.007950 s:  VX_ZONE_ERROR:Enabled
  3054.007956 s:  VX_ZONE_WARNING:Enabled
  3054.008811 s:  VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
  3054.009969 s:  VX_ZONE_INIT:[tivxHostInitLocal:93] Initialization Done for HOST !!!
network file: /opt/vision_apps/test_data/tivx/tidl_models/tidl_net_mobilenet_v1.bin
config  file: /opt/vision_apps/test_data/tivx/tidl_models/tidl_io_mobilenet_v1_1.bin
Iteration 0 of 1000000 ... 


 =================================
 Demo : TIDL Object Classification
 =================================

 p: Print performance statistics

 x: Exit

 Enter Choice: 



 =================================
 Demo : TIDL Object Classification
 =================================

 p: Print performance statistics

 x: Exit

 Enter Choice: 



 =================================
 Demo : TIDL Object Classification
 =================================

 p: Print performance statistics

 x: Exit

 Enter Choice: p


Summary of CPU load,
====================

CPU: mpu1_0: TOTAL LOAD =   3.57 % ( HWI =   0.18 %, SWI =   0.18 % )
CPU: mcu2_0: TOTAL LOAD =  25. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU: mcu2_1: TOTAL LOAD =  22. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU:  c6x_1: TOTAL LOAD =   0. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU:  c6x_2: TOTAL LOAD =   0. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )
CPU:  c7x_1: TOTAL LOAD =   0. 0 % ( HWI =   0. 0 %, SWI =   0. 0 % )


HWA performance statistics,
===========================



DDR performance statistics,
===========================

DDR: READ  BW: AVG =    204 MB/s, PEAK =   5754 MB/s
DDR: WRITE BW: AVG =     21 MB/s, PEAK =   2550 MB/s
DDR: TOTAL BW: AVG =    225 MB/s, PEAK =   8304 MB/s


Detailed CPU performance/memory statistics,
===========================================

DDR_SHARED_MEM: Alloc's: 21 alloc's of 30085913 bytes 
DDR_SHARED_MEM: Free's : 8 free's  of 4807312 bytes 
DDR_SHARED_MEM: Open's : 13 allocs  of 25278601 bytes 
DDR_SHARED_MEM: Total size: 536870912 bytes 

CPU: mcu2_0: TASK:           IPC_RX:   0. 0 %
CPU: mcu2_0: TASK:       REMOTE_SRV:   0. 0 %
CPU: mcu2_0: TASK:        LOAD_TEST:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CPU_0:   0. 0 %
CPU: mcu2_0: TASK:        TIVX_V1NF:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_V1LDC1:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_V1SC1:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_V1MSC2:   0. 0 %
CPU: mcu2_0: TASK:       TIVXVVISS1:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT1:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT2:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_DISP1:   0.26 %
CPU: mcu2_0: TASK:       TIVX_DISP2:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CSITX:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT3:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT4:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT5:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT6:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT7:   0. 0 %
CPU: mcu2_0: TASK:       TIVX_CAPT8:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_DPM2M1:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_DPM2M2:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_DPM2M3:   0. 0 %
CPU: mcu2_0: TASK:      TIVX_DPM2M4:   0. 0 %

CPU: mcu2_0: HEAP:    DDR_LOCAL_MEM: size =   16777216 B, free =   11235072 B ( 66 % unused)
CPU: mcu2_0: HEAP:           L3_MEM: size =     262144 B, free =     261888 B ( 99 % unused)

CPU: mcu2_1: TASK:           IPC_RX:   0. 0 %
CPU: mcu2_1: TASK:       REMOTE_SRV:   0. 0 %
CPU: mcu2_1: TASK:        LOAD_TEST:   0. 0 %
CPU: mcu2_1: TASK:       TIVX_CPU_1:   0. 0 %
CPU: mcu2_1: TASK:         TIVX_SDE:   0. 0 %
CPU: mcu2_1: TASK:         TIVX_DOF:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_RX:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU: mcu2_1: TASK:      IPC_TEST_TX:   0. 0 %

CPU: mcu2_1: HEAP:    DDR_LOCAL_MEM: size =   16777216 B, free =   16773376 B ( 99 % unused)
CPU: mcu2_1: HEAP:           L3_MEM: size =     262144 B, free =     262144 B (100 % unused)

CPU:  c6x_1: TASK:           IPC_RX:   0. 0 %
CPU:  c6x_1: TASK:       REMOTE_SRV:   0. 0 %
CPU:  c6x_1: TASK:        LOAD_TEST:   0. 0 %
CPU:  c6x_1: TASK:         TIVX_CPU:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_RX:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_1: TASK:      IPC_TEST_TX:   0. 0 %

CPU:  c6x_1: HEAP:    DDR_LOCAL_MEM: size =   16777216 B, free =   16773376 B ( 99 % unused)
CPU:  c6x_1: HEAP:           L2_MEM: size =     229376 B, free =     229376 B (100 % unused)
CPU:  c6x_1: HEAP:  DDR_SCRATCH_MEM: size =   50331648 B, free =   50331648 B (100 % unused)

CPU:  c6x_2: TASK:           IPC_RX:   0. 0 %
CPU:  c6x_2: TASK:       REMOTE_SRV:   0. 0 %
CPU:  c6x_2: TASK:        LOAD_TEST:   0. 0 %
CPU:  c6x_2: TASK:         TIVX_CPU:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_RX:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c6x_2: TASK:      IPC_TEST_TX:   0. 0 %

CPU:  c6x_2: HEAP:    DDR_LOCAL_MEM: size =   16777216 B, free =   16773376 B ( 99 % unused)
CPU:  c6x_2: HEAP:           L2_MEM: size =     229376 B, free =     229376 B (100 % unused)
CPU:  c6x_2: HEAP:  DDR_SCRATCH_MEM: size =   50331648 B, free =   50331648 B (100 % unused)

CPU:  c7x_1: TASK:           IPC_RX:   0. 0 %
CPU:  c7x_1: TASK:       REMOTE_SRV:   0. 0 %
CPU:  c7x_1: TASK:        LOAD_TEST:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P1:   0.20 %
CPU:  c7x_1: TASK:      TIVX_C71_P2:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P3:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P4:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P5:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P6:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P7:   0. 0 %
CPU:  c7x_1: TASK:      TIVX_C71_P8:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_RX:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %
CPU:  c7x_1: TASK:      IPC_TEST_TX:   0. 0 %

CPU:  c7x_1: HEAP:    DDR_LOCAL_MEM: size =  268435456 B, free =  248440320 B ( 92 % unused)
CPU:  c7x_1: HEAP:           L3_MEM: size =    8159232 B, free =          0 B (  0 % unused)
CPU:  c7x_1: HEAP:           L2_MEM: size =     458752 B, free =     458752 B (100 % unused)
CPU:  c7x_1: HEAP:           L1_MEM: size =      16384 B, free =          0 B (  0 % unused)
CPU:  c7x_1: HEAP:  DDR_SCRATCH_MEM: size =  385875968 B, free =  385344256 B ( 99 % unused)


GRAPH:   app_tidl_graph (#nodes =   1, #executions =      3)
 NODE:       DSP_C7-1:                 TIDLNode: avg =   1810 usecs, min/max =   1369 /   2693 usecs, #executi3

GRAPH:          Display (#nodes =   1, #executions =      3)
 NODE:       DISPLAY1:              DisplayNode: avg =  56978 usecs, min/max =  48711 /  64248 usecs, #executi3

 PERF:           FILEIO: avg =  22513 usecs, min/max =  14841 /  27517 usecs, #executions =          3
 PERF:             DRAW: avg =  14456 usecs, min/max =  11600 /  19927 usecs, #executions =          3
 PERF:            TOTAL: avg =  97557 usecs, min/max =  87259 / 104096 usecs, #executions =          3

 PERF:            TOTAL:   10.25 FPS



 =================================
 Demo : TIDL Object Classification
 =================================

 p: Print performance statistics

 x: Exit

 Enter Choice: 


 =================================
 Demo : TIDL Object Classification
 =================================

Regaeds,

Barry