• 状态 TI Thinks Resolved
  • 已锁定 已锁定
  • 个回复 11 个回复
  • 答案 1 答案
  • 名订阅用户 11 名订阅用户
  • 次查看 411 次查看
  • 用户 0 名在线用户
选项
选项
相关

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VL-Q1: OSPI read

chen qitian
Prodigy 20 points
Part Number: TDA4VL-Q1
Other Parts Discussed in Thread: TDA4VM

HI expert:

There has some questions about TDA4VL OSPI read and write：

The OSPI of TDA4VL was configured as Tap DDR mode. During the signal test, it was found that the Timing Requirements could be met, but the Switching Characteristics timing could not be met.

The software configuration is as follows:

P = CLK cycle time = SCLK period in ns = 20.75MHz ——ns：1/20.75*1000=48.19ns

M = OSPI_DEV_DELAY_REG[D_INIT_FLD] = 10

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]=10

R = refclk cycle time in ns = 166MHz——ns：1/166*1000=6ns

T =OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD] = 0

Using the above data and TDA4VL-Q1 to calculate O4 O5 O6, the results are as follows. The measurement timing cannot meet the requirements, but the communication is OK.See those  test pictures:

O4

td(CLK-CSn)

Delay time, CSn active edge to CLK rising edge

1.8V

0.475 * P +0.975 * M * R- 1 (2) (3) (5)

80.3915665

0.525 * P +1.025 * M * R+ 1(2) (3) (5)

82.80120505

ns

O5

td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive edge

1.8V

0.475 * P +0.975 * N * R- 1(2) (4) (5)

80.3915665

0.525 * P +1.025 * N * R+ 1 (2) (4) (5)

82.80120505

ns

O6

td(CLK-D)

Delay time, CLK active edge to D[i:0] transition(1)

1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX

-17.94 + 0.975*T*R

-17.94

-1.56 + 1.025*T*R

-1.56

ns

Two questions need to be answered:
① Does OSPI read refer to the Switching Characteristics sequence?
② The result calculated by the formula is too large, is it the problem of the formula？(I compared the TDA4VM specification, there is no such formula, and the parameters are not calculated to be so large)

Timing：

Switching Characteristics：

  • 0
    TI__Mastermind 27060 points

    Hello，

    chen qitian 说：
    ① Does OSPI read refer to the Switching Characteristics sequence?

    Yes, OSPI read operations do involve switching characteristics, especially the timing of signal transitions between different states. This includes the conversion between clock (CLK) and chip selection (CSn) signals, as well as the conversion between clock and data signals (D [i: 0]).

    chen qitian 说：
    ② The result calculated by the formula is too large, is it the problem of the formula

    Perhaps the formula you used is not entirely accurate

    Regards，

    Gary

  • 0 回复 Gary Lu
    Prodigy 20 points

    Hi expert:

    The formula is from TDA4VL-Q1,is not accurate?and how can i get the true formula,is it any update on the datasheet?

  • 0 回复 chen qitian
    TI__Mastermind 27060 points

    Hello，

    This is an errata, please refer to it：https://www.ti.com.cn/cn/lit/pdf/sprz530

    Regards，

    Gary

  • 0 回复 Gary Lu
    Prodigy 20 points

    Hi expert:

    I've checked the errata.There is no description of the problem.

    Software configuration parameter:

    P = CLK cycle time = SCLK period in ns = 20.75MHz
    M = OSPI_DEV_DELAY_REG[D_INIT_FLD] = 10
    N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]=10
    R = refclk cycle time in ns = 166666666
    T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD] =1

    Hold time, OSPI0/1_D[7:0] valid after active OSPI0/1_CLK edge

    (0.975T(1) (1.84 + R(2)))

    =7.69ns

    but we test is 4.68ns

    Is it the problem of the formula？Please give me the correct formula

  • 0 回复 chen qitian
    TI__Mastermind 27060 points

    Hold time=M×P+N×P+R+T

  • 0 回复 Gary Lu
    Prodigy 20 points

    Hi expert:

    This hold time formula is ok,

    and please give me the correct formula about delay time.

    P = CLK cycle time = SCLK period in ns = 20.75MHz
    M = OSPI_DEV_DELAY_REG[D_INIT_FLD] = 10
    N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]=10
    R = refclk cycle time in ns = 166666666
    T=OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD] = 0

  • 0 回复 chen qitian
    TI__Mastermind 27060 points

    Waiting for me to check and reply to you

  • 0 回复 chen qitian
    TI__Mastermind 27060 points

    (P = 20.75 MHz) This is the frequency; to find the period in nanoseconds (ns), you need to take the reciprocal and convert it to ns.
    (M = 10)
    (N = 10)
    (R = 166,666,666 ns) This value seems excessively large for a period in nanoseconds; typically, cycle times are much smaller. Please confirm this value.
    (T = 0)
    It appears you have the formulas for delay times \( t_{d(CSn-CLK)} \) and \( t_{d(CLK-D)} \). However, the formulas provided in the image are quite complex, and it is not immediately clear which part refers to the 'hold time' or 'delay time'.
    If we assume that the hold time formula is correct and you need the delay time formula, we could substitute the given values into the formulas from the image to calculate the delay times.
    However, there seems to be a misunderstanding with the variable R, as the value given (166,666,666 ns) is extremely high for a clock cycle time. If  R is indeed a cycle time, it should be a much smaller number, since typical clock cycles range from a few nanoseconds to several hundred nanoseconds. The current value of R translates to a period of over 166 seconds, which is not typical for a clock cycle duration. Could you confirm the correct value for R?

  • 0 回复 Gary Lu
    Prodigy 20 points

    P = CLK cycle time = SCLK period in ns = 20.75MHz=48.2ns
    M = OSPI_DEV_DELAY_REG[D_INIT_FLD] = 10
    N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]=10
    R = refclk cycle time in ns = 166666666Hz=166MHz=6.02ns

    T1 = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD] =1
    T2 =OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD] = 0

  • 0 回复 chen qitian
    TI__Mastermind 27060 points

    Please allow me to check, thank you

  • 0 回复 chen qitian
    TI__Mastermind 27060 points

    Hello，

    The recalculated delay time value is as follows:
    For O4 (CSn activation edge to CLK rising edge) and O5 (CLK rising edge to CSn non activation edge), as they have the same formula and both M and N are equal to 10:
    Minimum delay time (O4_min and O5_min): approximately 80.59 nanoseconds
    Maximum delay time (O4_max and O5_max): approximately 88.01 nanoseconds
    For O6 (CLK activation edge to D [i: 0] conversion), since T2 is 0, DDR reading the delay field does not affect the delay time. The result is:
    O6 minimum delay time: -17.94 nanoseconds
    O6 maximum delay time: -1.56 nanoseconds
    As with previous calculations, a negative value of O6 means that time is advanced rather than delayed, which is usually physically meaningless. This may indicate that the interpretation of the formula may be incorrect, there may be typing errors in the data manual, or there may be some additional background or compensation that was not captured by the formula itself.
    Considering the background provided by these formulas and ensuring that there is no other information that may affect their application. Given these results, if there are still differences or confusion, it is best to directly consult the manufacturer's technical support for clear clarification.

    Regards，

    Gary