TDA4VM: SPL startup error with firmware for R5f MCU1_0 core embeded in tispl.bin

Part Number: TDA4VM

We are facing some issues while trying to replace the default demo application(mcusw->mcuss_demos->profiling->can or  mcusw->mcuss_demos->profiling->cddipc)embedded in `tispl.bin` with another fw from SDK 9.0 (ti-processor-sdk-rtos-j721e-evm-09_00_00_02) like the compiled from any mcusw demo version (compiled to run in mcu1_0).

After generate the u-boot from Linux SDK 9.0 (ti-processor-sdk-rtos-j721e-evm-09_00_00_02) we set booting mode in DFU and pass the generated images, obtaining the following output after load the new `tispl.bin

1.The log of mcusw->mcuss_demos->profiling->can  as follows

U-Boot SPL 2023.04 (Apr 02 2024 - 10:29:21 +0800)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.6--v09.00.06 (Kool Koala)')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from MMC2
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Loading Environment from nowhere... OK

2.The log of mcusw->mcuss_demos->profiling->cddipc  as follows

U-Boot SPL 2023.04 (Apr 01 2024 - 14:53:34 +0800)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.6--v09.00.06 (Kool Koala)')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed -121
Trying to boot from MMC2
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Loading Environment from nowhere... OK
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty
NOTICE:  BL31: Built : 00:42:57, Jan 13 2023
I/TC:
I/TC: OP-TEE version: 3.20.0 (gcc version 11.3.0 (GCC)) #1 Fri Jan 20 15:42:54 UTC 2023 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.6--v09.00.06 (Kool Koala)')
I/TC: HUK Initialized
E/TC:0 0 k3_sec_proxy_verify_thread:108 Queue is busy
E/TC:0 0 k3_sec_proxy_recv:196 Thread SEC_PROXY_RESPONSE_THREAD verification failed. ret = -65523
E/TC:0 0 ti_sci_get_response:101 Message receive failed (-65523)
E/TC:0 0 ti_sci_do_xfer:150 Failed to get response (-65523)
E/TC:0 0 sa2ul_init:59 Failed to get SA2UL device
E/TC:0 0 call_initcalls:43 Initcall __text_start + 0x00067bf8 failed
I/TC: Primary CPU switching to normal world boot
E/TC:0 0
E/TC:0 0 Core data-abort at address 0x10 (translation fault)
E/TC:0 0  esr 0x96000005  ttbr0 0x9e898000   ttbr1 0x00000000   cidr 0x0
E/TC:0 0  cpu #0          cpsr 0x800003c4
E/TC:0 0  x0  0000000000000010 x1  0000000000000001
E/TC:0 0  x2  0000000000000000 x3  0000000000000000
E/TC:0 0  x4  000000009e86c000 x5  0000000000ffffff
E/TC:0 0  x6  0000000000000002 x7  000000009e8a0190
E/TC:0 0  x8  0000000000000020 x9  000000009e8a0190
E/TC:0 0  x10 0000000000000000 x11 0000000000000000
E/TC:0 0  x12 0000000000000000 x13 000000009e8618f0
E/TC:0 0  x14 0000000000000000 x15 0000000000000000
E/TC:0 0  x16 000000009e8149e4 x17 0000000000000000
E/TC:0 0  x18 0000000000000000 x19 000000009e8a2ca0
E/TC:0 0  x20 000000009e8a2ca8 x21 0000000000000007
E/TC:0 0  x22 000000009e878000 x23 000000009e878b50
E/TC:0 0  x24 0000000100000000 x25 0000000000000000
E/TC:0 0  x26 0000000000000000 x27 0000000000000000
E/TC:0 0  x28 0000000000000000 x29 000000009e8a2c30
E/TC:0 0  x30 000000009e80eb7c elr 000000009e80eb9c
E/TC:0 0  sp_el0 000000009e8a2c30
E/TC:0 0 TEE load address @ 0x9e800000
E/TC:0 0 Call stack:
E/TC:0 0  0x9e80eb9c
E/TC:0 0 Panic 'unhandled pageable abort' at core/arch/arm/kernel/abort.c:572 <abort_handler>
E/TC:0 0 TEE load address @ 0x9e800000
E/TC:0 0 Call stack:
E/TC:0 0  0x9e808b04
E/TC:0 0  0x9e815f88
E/TC:0 0  0x9e808260
E/TC:0 0  0x9e805584

  • @Cherry Zhou 请抽空反馈,谢谢

  • 1、在mcusw上进行开发,没看到答复。

    eg:mcusw->mcuss_demos->profiling->cddipc

    2、我修改mcusw/build/j721e/mcu1_0/linker_r5_freertos.lds和mcusw/mcuss_demos/profiling/cddIpc/main_rtos.c

    2.1、linker_r5_freertos.lds

    /*==========================*/
    /*     Linker Settings      */
    /*==========================*/
    
    --retain="*(.bootCode)"
    --retain="*(.startupCode)"
    --retain="*(.startupData)"
    --retain="*(.irqStack)"
    --retain="*(.fiqStack)"
    --retain="*(.abortStack)"
    --retain="*(.undStack)"
    --retain="*(.svcStack)"
    
    --fill_value=0
    --stack_size=0x4000
    --heap_size=0x8000
    --entry_point=_freertosresetvectors
    
    -stack  0x4000  /* SOFTWARE STACK SIZE */
    -heap   0x8000  /* HEAP AREA SIZE      */
    
    /*-------------------------------------------*/
    /*       Stack Sizes for various modes       */
    /*-------------------------------------------*/
    __IRQ_STACK_SIZE   = 0x1000;
    __FIQ_STACK_SIZE   = 0x0100;
    __ABORT_STACK_SIZE = 0x0100;
    __UND_STACK_SIZE   = 0x0100;
    __SVC_STACK_SIZE   = 0x0100;
    
    /*--------------------------------------------------------------------------*/
    /*                               Memory Map                                 */
    /*--------------------------------------------------------------------------*/
    --define FILL_PATTERN=0xFEAA55EF
    --define FILL_LENGTH=0x100
    MEMORY
    {
        VECTORS (X)                 : ORIGIN = 0x00000000 LENGTH = 0x00000040
    
        /*=================== MCU0_R5F_0 Local View ========================*/
        MCU0_R5F_TCMA  (X)          : ORIGIN = 0x00000040 LENGTH = 0x00007FC0
        /*MCU0_R5F_TCMB0 (RWIX)       : ORIGIN = 0x41010000 LENGTH = 0x00008000*/
        MCU0_R5F_TCMB_VECS       (X) : ORIGIN = 0x41010000 LENGTH = 0x00000040
        MCU0_R5F_TCMB            (X) : ORIGIN = 0x41010040 LENGTH = 0x00007FC0
    
        /*==================== MCU0_R5F_1 SoC View =========================*/
        MCU0_R5F1_ATCM (RWIX)       : ORIGIN = 0x41400000 LENGTH = 0x00008000
        MCU0_R5F1_BTCM (RWIX)       : ORIGIN = 0x41410000 LENGTH = 0x00008000
    
        /*========================J721E MCMS3 LOCATIONS ===================*/
        /*---------- J721E Reserved Memory for ARM Trusted Firmware -------*/
        MSMC3_ARM_FW  (RWIX)        : ORIGIN = 0x70000000 LENGTH = 0x00040000   /* 256KB       */
        MSMC3         (RWIX)        : ORIGIN = 0x70040000 LENGTH = 0x007B0000   /* 8MB - 320KB */
        /*------------- J721E Reserved Memory for DMSC Firmware -----------*/
        MSMC3_DMSC_FW (RWIX)        : ORIGIN = 0x707F0000 LENGTH = 0x00010000   /* 64KB        */
    
        DDR0    (RWIX)          : origin=0x80000000 length=0x8000000      /* 2GB */
    
        /* Used in this file */
        DDR0_MCU_1_0 (RWIX)     : origin=0x97000000 length=0x1000000       /* 16MB */
    
    
        /* Refer the user guide for details on persistence of these sections */
        OCMC_RAM_BOARD_CFG (RWIX)   : origin=0x41C80000 length=0x2000
        OCMC_RAM_SCISERVER (RWIX)   : origin=0x41C82000 length=0x60000
        OCMC_RAM (RWIX)             : origin=0x41CE2000 length=0x1DB00
        OCMC_RAM_X509_HEADER (RWIX) : origin=0x41CFFB00 length=0x500
    
        MCU1_0_IPC_DATA      (RWIX)	: origin=0xA0000000 length=0x00100000	/*   1MB */
        MCU1_0_EXT_DATA      (RWIX)	: origin=0xA0100000 length=0x00100000	/*   1MB */
        MCU1_O_RSF_MEM_TEXT  (RWIX) : origin=0xA0200000 length=0x00100000	/*   1MB */
        MCU1_0_R5F_MEM_DATA  (RWIX) : origin=0xA0300000 length=0x00100000	/*   1MB */
        MCU1_0_DDR_SPACE     (RWIX) : origin=0xA0400000 length=0x00C00000	/*   12MB */
    }  /* end of MEMORY */
    
    /*----------------------------------------------------------------------------*/
    /* Section Configuration                                                      */
    
    SECTIONS
    {
        .freertosrstvectors      : {} palign(8)      > MCU0_R5F_TCMB_VECS
        .bootCode        : {} palign(8)      > MCU0_R5F_TCMB
        .startupCode     : {} palign(8)      > MCU0_R5F_TCMB
        .startupData     : {} palign(8)      > MCU0_R5F_TCMB, type = NOINIT
        .text    	: {} palign(8) 		> MCU1_0_DDR_SPACE
        GROUP {
            .text.hwi    : palign(8)
            .text.cache  : palign(8)
            .text.mpu    : palign(8)
            .text.boot   : palign(8)
        }                           > MCU0_R5F_TCMB
        .const   	: {} palign(8) 		> MCU1_0_DDR_SPACE
        .rodata   : {} palign(8)    > MCU1_0_DDR_SPACE
        .cinit   	: {} palign(8) 		> MCU1_0_DDR_SPACE
        .pinit   	: {} palign(8) 		> MCU1_0_DDR_SPACE
    
        /* For NDK packet memory, we need to map this sections before .bss*/
        .bss:NDK_MMBUFFER  (NOLOAD) {} ALIGN (128) > MCU1_0_DDR_SPACE
        .bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > MCU1_0_DDR_SPACE
    
        .bss     	: {} align(4)  		> MCU1_0_DDR_SPACE
        .far     	: {} align(4)  		> MCU1_0_DDR_SPACE
        .data    	: {} palign(128) 	> MCU1_0_DDR_SPACE
        .data_buffer: {} palign(128) 	> MCU1_0_DDR_SPACE
    	  .sysmem  	: {} 				> MCU1_0_DDR_SPACE
    	  .stack  	: {} align(4)		> MCU1_0_DDR_SPACE  (HIGH) fill=FILL_PATTERN
        .bss.devgroup  : {*(.bss.devgroup*)} align(4)       > MCU1_0_DDR_SPACE
        .const.devgroup : {*(.const.devgroup*)} align(4)      > MCU1_0_DDR_SPACE
        .data_user      : {} align(4)      > MCU1_0_DDR_SPACE
        .boardcfg_data  : {} align(4)      > MCU1_0_DDR_SPACE
        /* USB or any other LLD buffer for benchmarking */
        .benchmark_buffer (NOLOAD) {} ALIGN (8) > MCU1_0_DDR_SPACE
    
        ipc_data_buffer (NOINIT) : {} palign(128)	> MCU1_0_DDR_SPACE
        .resource_table          : 
        {
            __RESOURCE_TABLE = .;
        }                                           > MCU1_0_EXT_DATA
    
        .tracebuf                : {} align(1024)   > MCU1_0_EXT_DATA
    
        .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > MCU1_0_DDR_SPACE(HIGH)
        RUN_START(__IRQ_STACK_START)
        RUN_END(__IRQ_STACK_END)
    
        .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > MCU1_0_DDR_SPACE(HIGH)
        RUN_START(__FIQ_STACK_START)
        RUN_END(__FIQ_STACK_END)
    
        .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > MCU1_0_DDR_SPACE(HIGH)
        RUN_START(__ABORT_STACK_START)
        RUN_END(__ABORT_STACK_END)
    
        .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > MCU1_0_DDR_SPACE(HIGH)
        RUN_START(__UND_STACK_START)
        RUN_END(__UND_STACK_END)
    
        .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > MCU1_0_DDR_SPACE(HIGH)
        RUN_START(__SVC_STACK_START)
        RUN_END(__SVC_STACK_END)
    
        /* Additional sections settings     */
        McalTextSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR_SPACE
        {
            .=align(4);
            __linker_spi_text_start = .;
            . += FILL_LENGTH;
            *(SPI_TEXT_SECTION)
            *(SPI_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_text_end = .;
    
            .=align(4);
            __linker_gpt_text_start = .;
            . += FILL_LENGTH;
            *(GPT_TEXT_SECTION)
            *(GPT_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_text_end = .;
    
            .=align(4);
            __linker_dio_text_start = .;
            . += FILL_LENGTH;
            *(DIO_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_text_end = .;
    
            .=align(4);
            __linker_eth_text_start = .;
            . += FILL_LENGTH;
            *(ETH_TEXT_SECTION)
            *(ETH_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_text_end = .;
    
            .=align(4);
            __linker_ethtrcv_text_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_text_end = .;
    
            .=align(4);
            __linker_can_text_start = .;
            . += FILL_LENGTH;
            *(CAN_TEXT_SECTION)
            *(CAN_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_text_end = .;
    
            .=align(4);
            __linker_wdg_text_start = .;
            . += FILL_LENGTH;
            *(WDG_TEXT_SECTION)
            *(WDG_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_text_end = .;
    
            .=align(4);
            __linker_pwm_text_start = .;
            . += FILL_LENGTH;
            *(PWM_TEXT_SECTION)
            *(PWM_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_text_end = .;
    
            __linker_adc_text_start = .;
            . += FILL_LENGTH;
            *(ADC_TEXT_SECTION)
            *(ADC_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_text_end = .;
    
            .=align(4);
            __linker_cdd_ipc_text_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_TEXT_SECTION)
            *(CDD_IPC_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_text_end = .;
    
            .=align(4);
            __linker_mcu_text_start = .;
            . += FILL_LENGTH;
            *(MCU_TEXT_SECTION)
            *(MCU_ISR_TEXT_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_mcu_text_end = .;
    
        }
        McalConstSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR_SPACE
        {
            .=align(4);
            __linker_spi_const_start = .;
            . += FILL_LENGTH;
            *(SPI_CONST_32_SECTION)
            *(SPI_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_const_end = .;
    
            .=align(4);
            __linker_gpt_const_start = .;
            . += FILL_LENGTH;
            *(GPT_CONST_32_SECTION)
            *(GPT_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_const_end = .;
    
            .=align(4);
            __linker_dio_const_start = .;
            . += FILL_LENGTH;
            *(DIO_CONST_32_SECTION)
            *(DIO_CONST_UNSPECIFIED_SECTION)
            *(DIO_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_const_end = .;
    
            .=align(4);
            __linker_can_const_start = .;
            . += FILL_LENGTH;
            *(CAN_CONST_8_SECTION)
            *(CAN_CONST_32_SECTION)
            *(CAN_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_const_end = .;
    
            .=align(4);
            __linker_eth_const_start = .;
            . += FILL_LENGTH;
            *(ETH_CONST_32_SECTION)
            *(ETH_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_const_end = .;
    
            .=align(4);
            __linker_ethtrcv_const_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_CONST_32_SECTION)
            *(ETHTRCV_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_const_end = .;
    
            .=align(4);
            __linker_wdg_const_start = .;
            . += FILL_LENGTH;
            *(WDG_CONST_32_SECTION)
            *(WDG_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_const_end = .;
    
            .=align(4);
            __linker_pwm_const_start = .;
            . += FILL_LENGTH;
            *(PWM_CONST_32_SECTION)
            *(PWM_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_const_end = .;
    
            .=align(4);
            __linker_adc_const_start = .;
            . += FILL_LENGTH;
            *(ADC_CONST_32_SECTION)
            *(ADC_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_const_end = .;
    
            .=align(4);
            __linker_cdd_ipc_const_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_CONST_32_SECTION)
            *(CDD_IPC_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_const_end = .;
    
            .=align(4);
            __linker_mcu_const_start = .;
            . += FILL_LENGTH;
            *(MCU_CONST_32_SECTION)
            *(MCU_CONFIG_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_mcu_const_end = .;
        }
    
        McalInitSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR_SPACE
        {
            .=align(4);
            __linker_spi_init_start = .;
            . += FILL_LENGTH;
            *(SPI_DATA_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_init_end = .;
    
            .=align(4);
            __linker_gpt_init_start = .;
            . += FILL_LENGTH;
            *(GPT_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_init_end = .;
    
            .=align(4);
            __linker_pwm_init_start = .;
            . += FILL_LENGTH;
            *(PWM_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_init_end = .;
    
            .=align(4);
            __linker_dio_init_start = .;
            . += FILL_LENGTH;
            *(DIO_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_init_end = .;
    
            .=align(4);
            __linker_eth_init_start = .;
            . += FILL_LENGTH;
            *(ETH_DATA_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_init_end = .;
    
            .=align(4);
            __linker_ethtrcv_init_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_DATA_INIT_UNSPECIFIED_SECTION)
            *(ETHTRCV_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_init_end = .;
    
            .=align(4);
            __linker_can_init_start = .;
            . += FILL_LENGTH;
            *(CAN_DATA_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_init_end = .;
    
            .=align(4);
            __linker_wdg_init_start = .;
            . += FILL_LENGTH;
            *(WDG_DATA_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_init_end = .;
    
            .=align(4);
            __linker_adc_init_start = .;
            . += FILL_LENGTH;
            *(ADC_DATA_INIT_UNSPECIFIED_SECTION)
            *(ADC_DATA_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_init_end = .;
    
            .=align(4);
            __linker_cdd_ipc_init_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_DATA_INIT_UNSPECIFIED_SECTION)
            *(CDD_IPC_DATA_INIT_32_SECTION)
            *(CDD_IPC_DATA_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_init_end = .;
    
            .=align(4);
    
            __linker_fls_init_start = .;
            . += FILL_LENGTH;
            *(FLS_DATA_INIT_UNSPECIFIED_SECTION)
            *(FLS_DATA_INIT_32_SECTION)
            *(FLS_DATA_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_fls_init_end = .;
    
            __linker_mcu_init_start = .;
            . += FILL_LENGTH;
            *(MCU_DATA_INIT_UNSPECIFIED_SECTION)
            *(MCU_DATA_INIT_32_SECTION)
            *(MCU_DATA_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_mcu_init_end = .;
    
        }
        McalNoInitSection : fill=FILL_PATTERN, align=4, load > MCU1_0_DDR_SPACE, type = NOINIT
        {
            .=align(4);
            __linker_spi_no_init_start = .;
            . += FILL_LENGTH;
            *(SPI_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_spi_no_init_end = .;
    
            .=align(4);
            __linker_gpt_no_init_start = .;
            . += FILL_LENGTH;
            *(GPT_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_gpt_no_init_end = .;
    
            .=align(4);
            __linker_dio_no_init_start = .;
            . += FILL_LENGTH;
            *(DIO_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_dio_no_init_end = .;
    
            .=align(4);
            __linker_eth_no_init_start = .;
            . += FILL_LENGTH;
            *(ETH_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_eth_no_init_end = .;
    
            .=align(4);
            __linker_ethtrcv_no_init_start = .;
            . += FILL_LENGTH;
            *(ETHTRCV_DATA_NO_INIT_UNSPECIFIED_SECTION)
            *(ETHTRCV_DATA_NO_INIT_16_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_ethtrcv_no_init_end = .;
    
            .=align(4);
            __linker_can_no_init_start = .;
            . += FILL_LENGTH;
            *(CAN_DATA_NO_INIT_UNSPECIFIED_SECTION)
            *(CAN_DATA_NO_INIT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_can_no_init_end = .;
    
            .=align(4);
            __linker_wdg_no_init_start = .;
            . += FILL_LENGTH;
            *(WDG_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_wdg_no_init_end = .;
    
            .=align(4);
            __linker_pwm_no_init_start = .;
            . += FILL_LENGTH;
            *(PWM_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_pwm_no_init_end = .;
    
            __linker_adc_no_init_start = .;
            . += FILL_LENGTH;
            *(ADC_DATA_NO_INIT_UNSPECIFIED_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_adc_no_init_end = .;
    
            __linker_cdd_ipc_no_init_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_DATA_NO_INIT_UNSPECIFIED_SECTION)
            *(CDD_IPC_DATA_NO_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_cdd_ipc_no_init_end = .;
    
            __linker_mcu_no_init_start = .;
            . += FILL_LENGTH;
            *(MCU_DATA_NO_INIT_UNSPECIFIED_SECTION)
            *(MCU_DATA_NO_INIT_8_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_mcu_no_init_end = .;
    
        }
        /* Example Utility specifics */
        VariablesAlignedNoInitSection : align=8, load > MCU1_0_DDR_SPACE, type = NOINIT
        {
            .=align(8);
            __linker_cdd_ipc_no_init_align_8b_start = .;
            . += FILL_LENGTH;
            *(CDD_IPC_DATA_NO_INIT_8_ALIGN_8B_SECTION)
            .=align(8);
            . += FILL_LENGTH;
            __linker_cdd_ipc_no_init_align_8b_end = .;
        }
        /* Example Utility specifics */
        UtilityNoInitSection : align=4, load > MCU1_0_DDR_SPACE, type = NOINIT
        {
            .=align(4);
            __linker_utility_no_init_start = .;
            . += FILL_LENGTH;
            *(EG_TEST_RESULT_32_SECTION)
            .=align(4);
            . += FILL_LENGTH;
            __linker_utility_no_init_end = .;
        }
        SciClientBoardCfgSection : align=128, load > MCU1_0_DDR_SPACE, type = NOINIT
        {
            .=align(128);
            __linker_boardcfg_data_start = .;
            . += FILL_LENGTH;
            *(.boardcfg_data)
            .=align(128);
            . += FILL_LENGTH;
            __linker_boardcfg_data_end = .;
        }
        /* This section is used for descs and ring mems. It's best to have
         * it in OCMRAM or MSMC3 */
        McalUdmaSection : fill=FILL_PATTERN, align=128, load > MCU1_0_DDR_SPACE
        {
            .=align(128);
            __linker_eth_udma_desc_start = .;
            . += FILL_LENGTH;
            *(ETH_UDMA_DESC_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_udma_desc_end = .;
    
            .=align(128);
            __linker_eth_udma_ring_start = .;
            . += FILL_LENGTH;
            *(ETH_UDMA_RING_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_udma_ring_end = .;
        }
        McalTxDataSection : fill=FILL_PATTERN, align=128, load > MCU1_0_DDR_SPACE, type = NOINIT
        {
            .=align(128);
            __linker_eth_tx_data_start = .;
            . += FILL_LENGTH;
            *(ETH_TX_DATA_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_tx_data_end = .;
        }
        McalRxDataSection : fill=FILL_PATTERN, align=128, load > MCU1_0_DDR_SPACE, type = NOINIT
        {
            .=align(128);
            __linker_eth_rx_data_start = .;
            . += FILL_LENGTH;
            *(ETH_RX_DATA_SECTION)
            .=align(128);
            . += FILL_LENGTH;
            __linker_eth_rx_data_end = .;
        }
    }  /* end of SECTIONS */
    
    /*----------------------------------------------------------------------------*/
    /* Misc linker settings                                                       */
    
    
    /*-------------------------------- END ---------------------------------------*/
    

    2.2、main_rtos.c

    /*
    *
    * Copyright (c) 2023 Texas Instruments Incorporated
    *
    * All rights reserved not granted herein.
    *
    * Limited License.
    *
    * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
    * license under copyrights and patents it now or hereafter owns or controls to make,
    * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
    * terms herein.  With respect to the foregoing patent license, such license is granted
    * solely to the extent that any such patent is necessary to Utilize the software alone.
    * The patent license shall not apply to any combinations which include this software,
    * other than combinations with devices manufactured by or for TI ("TI Devices").
    * No hardware patent is licensed hereunder.
    *
    * Redistributions must preserve existing copyright notices and reproduce this license
    * (including the above copyright notice and the disclaimer and (if applicable) source
    * code license limitations below) in the documentation and/or other materials provided
    * with the distribution
    *
    * Redistribution and use in binary form, without modification, are permitted provided
    * that the following conditions are met:
    *
    * *       No reverse engineering, decompilation, or disassembly of this software is
    * permitted with respect to any software provided in binary form.
    *
    * *       any redistribution and use are licensed by TI for use only with TI Devices.
    *
    * *       Nothing shall obligate TI to provide you with source code for the software
    * licensed and provided to you in object code.
    *
    * If software source code is provided to you, modification and redistribution of the
    * source code are permitted provided that the following conditions are met:
    *
    * *       any redistribution and use of the source code, including any resulting derivative
    * works, are licensed by TI for use only with TI Devices.
    *
    * *       any redistribution and use of any object code compiled from the source code
    * and any resulting derivative works, are licensed by TI for use only with TI Devices.
    *
    * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
    *
    * may be used to endorse or promote products derived from this software without
    * specific prior written permission.
    *
    * DISCLAIMER.
    *
    * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
    * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
    * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
    * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
    * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
    * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
    * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
    * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
    * OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    */
    
    /**
     *  \file main_rtos.c
     *
     *  \brief Main file for TI-RTOS build, initializes IPC for profiling
     */
    
    /* ========================================================================== */
    /*                             Include Files                                  */
    /* ========================================================================== */
    
    #include <ti/csl/arch/csl_arch.h>
    #include <ti/csl/soc.h>
    #include <ti/csl/cslr.h>
    
    #include <ti/osal/osal.h>
    #include <ti/osal/TaskP.h>
    
    #include "cddIpc_profile.h"
    
    #include "SchM_Cdd_Ipc.h" /* Exclusive area */
    
    #if (defined (BUILD_MCU1_0) && (defined (SOC_J721E) || defined (SOC_J7200)))
    #include <ti/drv/sciclient/sciserver_tirtos.h>
    #endif
    
    #include <ti/board/board.h>
    
    /* ========================================================================== */
    /*                           Macros & Typedefs                                */
    /* ========================================================================== */
    
    /* Test application stack size */
    #define APP_TASK_STACK                  (10U * 1024U)
    /**< Stack required for the stack */
    #define IPC_PROFILE_DEMO_TASK_NAME      ("CDD IPC PROFILE")
    /**< Task name */
    
    /* ========================================================================== */
    /*                         Structure Declarations                             */
    /* ========================================================================== */
    
    /* None */
    
    /* ========================================================================== */
    /*                          Function Declarations                             */
    /* ========================================================================== */
    static void Cdd_IpcProfile_PrintVersion(void);
    static void Cdd_IpcProfile_TaskFxn(void* a0, void* a1);
    sint32 SetupSciServer(void);
    /**< Initialize SCI Server, to process RM/PM Requests by other cores */
    /* ========================================================================== */
    /*                            Global Variables                                */
    /* ========================================================================== */
    /* application stack */
    static uint8_t Cdd_IpcProfile_TaskStack[APP_TASK_STACK] __attribute__((aligned(32)));
    /**< Stack for the task */
    
    Board_initCfg boardCfg = BOARD_INIT_MODULE_CLOCK | BOARD_INIT_PINMUX_CONFIG;
    
    /* ========================================================================== */
    /*                          Function Definitions                              */
    /* ========================================================================== */
    
    int main(void)
    {
        TaskP_Handle task;
        TaskP_Params taskParams;
        sint32 ret = CSL_PASS;
        /* Relocate FreeRTOS Reset Vectors from BTCM*/
        void _freertosresetvectors (void);
        memcpy((void *)0x0, (void *)_freertosresetvectors, 0x40);
        
        OS_init();
    
        Board_init(boardCfg);
    #ifdef UART_ENABLED
        AppUtils_Init();
    #endif
    
        /* Initialize SCI Client Server */
        ret = SetupSciServer();
        if(ret != CSL_PASS)
        {
            OS_stop();
        }
        AppUtils_LogResult(APP_UTILS_TEST_STATUS_INIT);
    
        Cdd_IpcProfile_Startup();
    
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "\n");
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
                                " IPC Profile Application - STARTS !!! \n");
    
        Cdd_IpcInit();
        /* No error checks required, as Det are turned OFF */
    
        Cdd_IpcProfile_PrintVersion();
    
    
        /* Initialize the task params */
        TaskP_Params_init(&taskParams);
        //taskParams.instance->name = IPC_PROFILE_DEMO_TASK_NAME;
        /* Set the task priority higher than the default priority (1) */
        taskParams.priority     = 3;
        taskParams.stack        = Cdd_IpcProfile_TaskStack;
        taskParams.stacksize    = sizeof (Cdd_IpcProfile_TaskStack);
    
        task = TaskP_create(&Cdd_IpcProfile_TaskFxn, &taskParams);
        if(NULL == task)
        {
            OS_stop();
        }
        OS_start();
    
        return(0);
    }
    
    
    static void Cdd_IpcProfile_TaskFxn(void* a0, void* a1)
    {
        Utils_prfInit();
    
        Utils_prfLoadRegister (TaskP_self(), IPC_PROFILE_DEMO_TASK_NAME);
    
        TaskP_yield();
    
        Cdd_IpcProfileTest();
    
        Utils_prfLoadUnRegister (TaskP_self());
        Utils_prfDeInit();
        return;
    }
    
    
    /** \brief prints of the version of this implementation */
    static void Cdd_IpcProfile_PrintVersion(void)
    {
    #if (STD_ON == CDD_IPC_VERSION_INFO_API)
        Std_VersionInfoType versioninfo;
    
        Cdd_IpcGetVersionInfo(&versioninfo);
        AppUtils_Printf(MSG_NORMAL, " \n");
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME " CDD IPC MCAL Version Info\n");
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "---------------------\n");
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME " Vendor ID           : %d\n",
                                                    versioninfo.vendorID);
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME " Module ID           : %d\n",
                                                    versioninfo.moduleID);
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME " SW Major Version    : %d\n",
                                                    versioninfo.sw_major_version);
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME " SW Minor Version    : %d\n",
                                                    versioninfo.sw_minor_version);
        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME " SW Patch Version    : %d\n",
                                                    versioninfo.sw_patch_version);
        AppUtils_Printf(MSG_NORMAL, " \n");
    #endif
    
    }
    
    sint32 SetupSciServer(void)
    {
        sint32 ret = CSL_PASS;
    #if (defined (BUILD_MCU1_0) && (defined (SOC_J721E) || defined (SOC_J7200)))
        Sciserver_TirtosCfgPrms_t appPrms;
        Sciclient_ConfigPrms_t clientPrms;
    
        appPrms.taskPriority[SCISERVER_TASK_USER_LO] = 1;
        appPrms.taskPriority[SCISERVER_TASK_USER_HI] = 4;
    
        /* Sciclient needs to be initialized before Sciserver. Sciserver depends on
         * Sciclient API to execute message forwarding */
        ret = Sciclient_configPrmsInit(&clientPrms);
        if (ret == CSL_PASS)
        {
            ret = Sciclient_init(&clientPrms);
        }
    
        if (ret == CSL_PASS)
        {
            ret = Sciserver_tirtosInit(&appPrms);
        }
    
        if (ret == CSL_PASS)
        {
            AppUtils_Printf(MSG_NORMAL, "Starting Sciserver..... PASSED\n");
        }
        else
        {
            AppUtils_Printf(MSG_NORMAL, "Starting Sciserver..... FAILED\n");
        }
    
    #endif
        return ret;
    }
    
    /*EoF*/
    

    3、将cdd_ipc_profile_app_freertos_mcu1_0_release_strip.xer5f作为编译u-boot-a72 的DM

    4、查看u-boot_build/a72中的tispl.bin内容

    5、上电启动后,soc串口log信息,如下,但mcu串口无log信息

    U-Boot SPL 2023.04 (Apr 10 2024 - 09:33:41 +0800)
    SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.6--v09.00.06 (Kool Koala)')
    EEPROM not available at 0x50, trying to read at 0x51
    Reading on-board EEPROM at 0x51 failed -121
    Trying to boot from MMC2
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
    Loading Environment from nowhere... OK
    Starting ATF on ARM64 core...
    
    NOTICE:  BL31: v2.8(release):v2.8-226-g2fcd408bb3-dirty
    NOTICE:  BL31: Built : 00:42:57, Jan 13 2023
    I/TC:
    I/TC: OP-TEE version: 3.20.0 (gcc version 11.3.0 (GCC)) #1 Fri Jan 20 15:42:54 UTC 2023 aarch64
    I/TC: WARNING: This OP-TEE configuration might be insecure!
    I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
    I/TC: Primary CPU initializing
    I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.6--v09.00.06 (Kool Koala)')
    I/TC: HUK Initialized
    E/TC:0 0 k3_sec_proxy_verify_thread:108 Queue is busy
    E/TC:0 0 k3_sec_proxy_recv:196 Thread SEC_PROXY_RESPONSE_THREAD verification failed. ret = -65523
    E/TC:0 0 ti_sci_get_response:101 Message receive failed (-65523)
    E/TC:0 0 ti_sci_do_xfer:150 Failed to get response (-65523)
    E/TC:0 0 sa2ul_init:59 Failed to get SA2UL device
    E/TC:0 0 call_initcalls:43 Initcall __text_start + 0x00067bf8 failed
    I/TC: Primary CPU switching to normal world boot
    E/TC:0 0
    E/TC:0 0 Core data-abort at address 0x10 (translation fault)
    E/TC:0 0  esr 0x96000005  ttbr0 0x9e898000   ttbr1 0x00000000   cidr 0x0
    E/TC:0 0  cpu #0          cpsr 0x800003c4
    E/TC:0 0  x0  0000000000000010 x1  0000000000000001
    E/TC:0 0  x2  0000000000000000 x3  0000000000000000
    E/TC:0 0  x4  000000009e86c000 x5  0000000000ffffff
    E/TC:0 0  x6  0000000000000002 x7  000000009e8a0190
    E/TC:0 0  x8  0000000000000020 x9  000000009e8a0190
    E/TC:0 0  x10 0000000000000000 x11 0000000000000000
    E/TC:0 0  x12 0000000000000000 x13 000000009e8618f0
    E/TC:0 0  x14 0000000000000000 x15 0000000000000000
    E/TC:0 0  x16 000000009e8149e4 x17 0000000000000000
    E/TC:0 0  x18 0000000000000000 x19 000000009e8a2ca0
    E/TC:0 0  x20 000000009e8a2ca8 x21 0000000000000007
    E/TC:0 0  x22 000000009e878000 x23 000000009e878b50
    E/TC:0 0  x24 0000000100000000 x25 0000000000000000
    E/TC:0 0  x26 0000000000000000 x27 0000000000000000
    E/TC:0 0  x28 0000000000000000 x29 000000009e8a2c30
    E/TC:0 0  x30 000000009e80eb7c elr 000000009e80eb9c
    E/TC:0 0  sp_el0 000000009e8a2c30
    E/TC:0 0 TEE load address @ 0x9e800000
    E/TC:0 0 Call stack:
    E/TC:0 0  0x9e80eb9c
    E/TC:0 0 Panic 'unhandled pageable abort' at core/arch/arm/kernel/abort.c:572 <abort_handler>
    E/TC:0 0 TEE load address @ 0x9e800000
    E/TC:0 0 Call stack:
    E/TC:0 0  0x9e808b04
    E/TC:0 0  0x9e815f88
    E/TC:0 0  0x9e808260
    E/TC:0 0  0x9e805584
    

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