UC2845: Technical Support Needed: UC2845 Startup Hiccup and Gate Drive Signal Distortion in Flyback Converter

Part Number: UC2845

Dear TI Support Team,

I am currently designing a Flyback converter using the UC2845 PWM controller. I am encountering some abnormal behaviors during the startup phase and would appreciate your professional insights.

System Specifications:

  • Controller: UC2845

  • Switch: MOSFET (1500V, 2.5A)

  • Target Output: 24V Adaptor

  • Vcc Source: External 15V DC Supply (for testing purposes)

  • Gate Resistor (Rg): 260 ohms

Issues Observed:

  1. Startup Hiccup (Blanking Period): Even with a stable external 15V Vcc, there is a significant "blanking period" (approx. 50-100ms) where the PWM output stops before restarting. I suspect it might be related to the ISEN (Pin 3) protection being triggered by inrush current or noise.

  2. Gate Drive Distortion: As shown in the attached waveforms (CH2: VGS), the gate drive signal is severely distorted with heavy ringing. The peak VGS is lower than expected, and the MOSFET seems to struggle to fully enter the linear (ohmic) region, staying too long in the saturation region.

  3. High Voltage Spike: The VDS spike reaches 1.4kV, which is very close to the MOSFET's 1.5kV rating.

Experimental Setup & Attachments:

  • Schematic: Full circuit diagram of the Flyback converter.

  • Test Condition: Please note that for the attached waveforms, I have connected two additional resistors (same ohmic value as the original) in parallel within the RCD Snubber network to evaluate the impact on the VDS spike.

  • Waveforms: Oscilloscope captures showing VDSVGSVCCFB and ISEN signals during startup.

    • CH1 (Yellow): VDS (showing the 1.25kV spike)

    • CH2 (Cyan): VGS (showing drive distortion)

    • CH3 (Purple): VCC

    • CH4 (Blue): FB or ISEN

Questions:

  1. What could be the primary cause of the long blanking period despite a stable Vcc?

  2. Based on the schematic, are there any recommendations for the ISEN filter (RC) or Gate Drive circuit to improve signal integrity and reduce ringing?

  3. Do you recommend any specific adjustments to the RCD Snubber or Soft-start to mitigate the 1.4kV startup spike?

Thank you for your time and assistance. I look forward to your reply.

Best regards,

JIANWEI WU

新代科技/台灣新代 SYNTEC

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  • 您好,

    已经收到了您的案例,调查需要些时间,感谢您的耐心等待。

  • 您的查询正在审核中。

  • 你好,

    尽管 Vcc 稳定,但消隐期过长的主要原因可能是什么?

    COMP引脚在此期间可能为低电平。这是唯一会导致开关失效的因素。请将VCC波形替换为COMP引脚波形,并记录相同的启动行为。

    请您再检查一下光耦合器到FB引脚的连接。您的电路图连接与数据手册中的参考电路图不符:

    根据原理图,对于ISEN滤波器(RC)栅极驱动电路,是否有任何建议可以改善信号完整性并减少振铃?

    您观察到的振铃现象可能是由于测量方式造成的。如果您使用的是带有长接地回路的示波器探头,则可能会引入额外的寄生电感,从而加剧振铃现象。此外,您当前的栅极电阻相当高,您可以尝试将其降低到几十欧姆。

    您是否建议对剩余电流动作保护器(RCD)的缓冲电路软启动电路进行任何特定的调整,以减轻1.4kV的启动尖峰电压?

    反激式变压器的漏感很可能是导致 MOSFET 关断时出现高频振铃的原因。当 FET 关断时,漏感中的电流能量会根据公式 V = L di/dt 产生振铃。如果您想解决振铃问题,建议从根源入手,即变压器的漏感。

    要降低RCD缓冲电路的钳位电压,您需要降低总电阻。目前您的电阻约为310kΩ,您可以尝试降低这个电阻值。

    关于软启动,您的原理图中没有软启动电路。建议您按照数据手册 7.3.10 节所示添加一个。