Job Title: Layout Engineer
Job ID: 9688BR
Application via TI Career Website: https://xjobs.brassring.com/1033/asp/tg/cim_jobdetail.asp?partnerid=25329&siteid=5227&areq=9688BR
In this position, you will be responsible for supporting product design and development through the development and preparation of multidimensional mixed-signal layouts of semiconductor ICs from schematics and related instructions provided by design engineering. The primary products will be completed using the Cadence software suite. IC blocks are analog/digital mixed-signal but contain significant analog and power content. The position will require knowledge of the entire design flow including front-end design and back-end verification including back-annotation. It requires active participation in project planning including schedule development and progress tracking. Lastly, the majority of your workday will be in front of a computer, though reasonable ergonomic needs will be accommodated.
Minimum requirements are:
• Major in Microelectronics or equivalent with 5-10 years of direct experience. BSEE is a plus.
• Demonstrated ability to interpret mixed-signal IC schematics, specifications, guidelines, or manuals. Basic knowledge of fundamental analog circuitry such as bandgap regulators, current mirrors, op amps, and comparators is required.
• Working knowledge of Cadence Virtuoso XL, Assura, and Skill scripting. You will be involved with front-end (design) and back-end (verification, back-annotation) activities.
• Extensive experience with analog, mixed-signal, and digital logic design flows including auto place and route.
• Knowledge of top-level floor planning techniques and appropriate placement of power, analog, and digital circuitry as well as metal power busses and ESD structures.
• Ability to independently lead mask design projects and support project management efforts.
• Ability to communicate with peers or engineers, in English, to resolve layout related problems including tool issues.
• Desire to support and contribute to continual design flow improvement.