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DSP TMDXEVM6678L Layout

During our schematic design of this multi-core DSP, following questions are found and does not know how to solve:

In our design, we would like to use the FPGA to boot-up the DSP. As we would provide a single 4x lane SRIO communication link (3.125Gbps) for them, we want to use SRIO boot-up.

However, we found that the SRIO boot device configuration (section 2.5.2.2. of datasheet) shows that the device can only support either 4 unit of 1x lane or 2 unit of 2x lane.

Also, we would like to provide the 100MHz reference clock to the SRIO module but found SRIO boot device configuration does not provide such setting.

(Our FPGA cannot re-configure its SRIO module again to support 1x and 4x SRIO at the same time.)

Does that mean we cannot use SRIO boot-up in such case?

In order to provide a boot method to our DSP, we would like to use the I2C master boot to update the SRIO boot mode parameter table. Then, we can use the 100MHz reference clock to configure 4x lane of 3.125Gbps SRIO for download DSP firmware from FPGA.

But we are not sure whether it is work or not. Can you help to provide a detail description for this method? And what should be setting on the DSP hardware (I2C boot mode)?

In the reference schematic of C6678 EVM board, the DDR3 reference clock is 66.6667MHz. Can we use 100MHz as the reference clock for DDR3 PLL inside the DSP?

Any relationship required for this DDR3 reference clock and DSP core reference clock required? (such as same source, frequency within certain ppm, etc.)

  • 1. 如果采用SRIO直接boot,是无法选用4x mode的,只能使用1x 或者2x mode;

    2. 如果使用SRIO,serdes的参考时钟是无法使用100M的,只能选取特定频率,详细情况参考SRIO user guide 和hardware desig guide

    3. 如果使用I2C先启动,随后转到FPGA做2次boot,是可以的,你可以参考下面的例子

    4. DDR3的锁相环是可以配置的,只要满足ref / (PLLD + 1)  * (PLLM + 1) = 1333M,  PLLD = 2, PLLM = 29即可

    I2C_Secondary_boot_release_Ver_0_1.zip
  • Hi dana

    I2C can configure it. you should choose I2C master boot (if you have EEPROM), and then modify the boot parameter table to suit SRIO boot mode. then branch the bootloader address again.

    4 steps :

    1, choose I2C master boot

    2, create a project which can configure a SRIO boot parameter table and then branch to bootloader  again, build it and get the .out file

    3, use the I2C boot mode to boot the DSP with the .out file

    4, begin the SRIO boot

    for more detail about the step 2:

    (1) the struct of SRIO boot parameter table you can get from document below:

    www.ti.com/.../sprugy5a.pdf

    (2) the address of boot parameter table is 0x10873680

    (3) the bootloader address is 0x20b00008

    Remarks:

    Reference clock of SRIO boot is 156.25MHz or 250MHz or 312.25MHz, and I'm not sure that the SRIO can work in 100MHz