During our schematic design of this multi-core DSP, following questions are found and does not know how to solve:
In our design, we would like to use the FPGA to boot-up the DSP. As we would provide a single 4x lane SRIO communication link (3.125Gbps) for them, we want to use SRIO boot-up.
However, we found that the SRIO boot device configuration (section 2.5.2.2. of datasheet) shows that the device can only support either 4 unit of 1x lane or 2 unit of 2x lane.
Also, we would like to provide the 100MHz reference clock to the SRIO module but found SRIO boot device configuration does not provide such setting.
(Our FPGA cannot re-configure its SRIO module again to support 1x and 4x SRIO at the same time.)
Does that mean we cannot use SRIO boot-up in such case?
In order to provide a boot method to our DSP, we would like to use the I2C master boot to update the SRIO boot mode parameter table. Then, we can use the 100MHz reference clock to configure 4x lane of 3.125Gbps SRIO for download DSP firmware from FPGA.
But we are not sure whether it is work or not. Can you help to provide a detail description for this method? And what should be setting on the DSP hardware (I2C boot mode)?
In the reference schematic of C6678 EVM board, the DDR3 reference clock is 66.6667MHz. Can we use 100MHz as the reference clock for DDR3 PLL inside the DSP?
Any relationship required for this DDR3 reference clock and DSP core reference clock required? (such as same source, frequency within certain ppm, etc.)