AWR1642 ：关于1642复位问题

你好，

请问你是怎么操作复位的呢?

你好 ，我是将1642的dss关闭后再往 地址 0xFFFFFF04里面写入 0xAD

具体代码如下：

#define READ_REG(reg, regVal)       regVal = *((uint32_t*)reg)

#define WRITE_REG(reg, regVal)      *((uint32_t*)reg) = regVal;

#define CORE_RST_REG                (0xFFFFFF04)

void softReset(void)

{

    uint32_t rstRegVal = 0;

    /* MSS core reset */

    READ_REG(CORE_RST_REG, rstRegVal);

    /* Write 0xAD in 0-7 bits to perform MSS core reset */

    rstRegVal &= ~0xFF;

    rstRegVal |= 0xAD;

    WRITE_REG(CORE_RST_REG, rstRegVal);

    return;

}

你好，

你可以直接使用#define CORE_RST_REG                (0xFFFFE100+0x1c)

Warm Reset Soft Reset, Watch Dog
Reset, Device Pin
WARM_RESET pin
This is an active low warm reset internally generated by
the device, or triggered by device pin WARM_RESET.
A write to the TOP_RCM.SOFTSYSRST register or
watch dog module can generate this reset; additionally,
the external pin WARM_RESET can also be used to
trigger this reset. Selection is controlled through the
TOP_RCM.MISCTL1 register.
The WARM_RESET pin is an open-drain failsafe IO
which can be used to reset the device from the external
world or to report the reset to the external world if it is
generated by an internal source such as watchdog.
A write to the TOP_RCM.SOFTSYSRST, as explained
in register description, can create this reset.
The watch dog module in the master subsystem can be
configured to trigger this reset. Check the watch dog
module description for details. This feature is enabled by
the TOP_RCM. WDRSTEN register.