请按照下面DCA1000EVM user guide里的troubleshooting加大delay试试。
The default Ethernet delay is pre-programmed as 25 µs in both the FPGA and software. The user can configure the delay from 5 µs to 500 µs, depending on the host PC configuration and capabilities, to avoid packet loss or packets out of sequence. Lower delay allows for higher bandwidth while increasing the probability of UDP packet drops at the PC end. Refer to Table 19 for the relationship between the packet delay and ethernet throughput. www.ti.com/.../spruij4a.pdf
