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CORTEX M4技术问题请教

aiqin he1
Expert 1360 points


请教：如何配置：PORT K；PORTL；PORTM；PORTN；PORTP等（AHB）端口：想做IO输出使用。#include "inc/lm4f232h5qd.h"里面没有Port(K/L/M/N/P)  Clock Gating Control的定义,自己加入后也不行？

  • 0
    Intellectual 985 points

    这个器件头文件中没有PORT K..P，那说明没有那么多GPIO。你软件上加入有什么用啊？需要硬件支持才行啊。

  • 0 回复 flora
    Expert 1360 points

    芯片是有这个资料的

  • 0 回复 aiqin he1
    Intellectual 985 points

    不好意思，我刚才没有看datasheet。

    Datasheet上说：Note that GPIO ports K, L, M, N, P, and Q can only be accessed through the AHB aperture.

    也就是说这几个port口只能通过AHB方式访问。

    没有用过M4，不过GPIO_PORTK_BASE应该定义在hw_memmap.h文件中吧

     

  • 0
    Expert 2914 points

    ROM_SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral);

  • 0 回复 Maojun
    Expert 1850 points

    详见规格书(LM4F232H5QD.pdf 第682页)

    10.3 Initialization and Configuration

    The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the

    Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other

    aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides

    better back-to-back access performance than the APB bus. These apertures aremutually exclusive.

    The aperture enabled for a given GPIO port is controlled by the appropriate bit in the GPIOHBCTL

    register (see page 286). Note that GPIO ports K, L, M, N, P, and Q can only be accessed through

    the AHB aperture.

    To use the pins in a particular GPIO port, the clock for the port must be enabled by setting the

    appropriate GPIO Port bit field (GPIOn) in the RCGCGPIO register (see page 389).

    When the internal POR signal is asserted and until otherwise configured, all GPIO pins are configured

    to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0, except for

    the pins shown in Table 10-1 on page 674. Table 10-3 on page 683 shows all possible configurations