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; Copyright (c) 2012, Texas Instruments Incorporated
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; --/COPYRIGHT--
;******************************************************************************
; MSP430x2274 Glasbreakage Detector
;
;
; MSP430x2274
; -----------------------
; JTAG <--|SBWTCK/TEST P1.7/TDO|-->
; <--|DVcc P1.6/TDI|--> SFD
; <--|P2.5/Rosc P1.5/TMS|--> CCA
; <--|DVSS P1.4/TCK|--> FIFOP
; Xout <--|P2.7 P1.3 |--> FIFO
; Xin <--|P2.6 P1.2 |--> VREG_EN
; <--|RST/SBWTDIO P1.1 |--> RESETCC
; OA0I0 -->|P2.0 P1.0 |--> LED
; OA0O <--|P2.1 P2.4 |--> VREF+/OFFSET
; OA0I1 -->|P2.2 P2.3 |-->
; CSN <--|P3.0 P3.7 |--> BUZZER
; SI <--|P3.1 P3.6 |-->
; SO <--|P3.2 P3.5 |--> UCA0BXD
; SCLK <--|P3.3 P3.4 |--> UCA0TXD
; <--|AVss P4.7 |-->
; <--|AVcc P4.6 |<-- OA1I3
; Vcc_Mic <--|P4.0 P4.5 |-->
; <--|P4.1 P4.4 |--> OA1O
; <--|P4.2 P4.3 |-->
; -----------------------
; R.Kammel
; Texas Instruments Inc.
; September 2006
; Built with IAR Embedded Workbench Version: 3.41A
; Code Version 1.001
;******************************************************************************
#include <msp430x22x4.h>
;-------------------------------------------------------------------------------
; Defines and Equals -
;-------------------------------------------------------------------------------
TACCR0_2ms EQU 20 ; TACCR0 = 20 @ VLO=12khz
trigger_lvl_high EQU 90 ; signal input level
trigger_lvl_low EQU -40 ; signal input level
#define integ_total R15
#define avg_temp_1 R14
#define res_avg R13
#define delay1 R12
#define inp13 R11
#define inp11 R10
#define INPUT R9
#define avg_1 R8
#define avg_2 R7
#define avg_3 R6
#define temp2 R5
#define temp1 R4
;-------------------------------------------------------------------------------
; Variables -
;-------------------------------------------------------------------------------
RSEG DATA16_Z
OUTP DS 2 ; allocate 2 Byte
inp21 DS 2
outp11 DS 2
outp21 DS 2
inp23 DS 2
outp13 DS 2
outp23 DS 2
inp15 DS 2
inp25 DS 2
outp15 DS 2
outp25 DS 2
p11 DS 2
p13 DS 2
p15 DS 2
delay2 DS 2
delay3 DS 2
delay4 DS 2
avg_temp_2 DS 2 ; averaging result n-2
peaks DS 2 ; captures number of peaks
zeros DS 2 ; captures number of zero crossings
integ_total_2 DS 2 ; result integral total signal
integ_HPB DS 2 ; result integral high pass signal
sample_count DS 2 ; captures number of samples
sample_count_2 DS 2
div_count_1 DS 2 ; overflow count if integ_total
div_count_2 DS 2 ; overflow count if integ_HPB
ratio_false DS 2 ; count failure ratio rule
peak_false DS 2 ; count failure peaks rule
zero_false DS 2 ; count failure zero crossing rule
AAF_select DS 2 ; select anti aliasing filter
;-------------------------------------------------------------------------------
; Main
;-------------------------------------------------------------------------------
RSEG CSTACK ; define stack segment
;-------------------------------------------------------------------------------
RSEG CODE ; assemble to Flash memory
;-------------------------------------------------------------------------------
RESET mov.w #SFE(CSTACK),SP ; initialize stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; stop WDT
SetupBC_ call #SetDCO_8Mhz
SetupP1 mov.b #0FFh,&P1DIR ; all P1.x outputs
clr.b &P1OUT ; all P1.x reset
SetupP2 mov.b #0FFh,&P2DIR ; all ports output, P2.0 don't care, P2.2 don't care,
mov.b #BIT0+BIT1+BIT2, &ADC10AE0
; P2.0 OA0I0, P2.1 OA0O (ADC IN)
; P2.2 OA0I1
clr.b &P2OUT ; all P2.x reset
SetupP3 mov.b #0FFh,&P3DIR ; all P3.x outputs
clr.b &P3OUT ; all P3.x reset
SetupP4 mov.b #0FFh,&P4DIR ; all P4.x output, P4.6 don't care, P4.4 don't care
clr.b &P4OUT ; all P4.x reset
mov.w #0, AAF_select ; select AAF, "0" off else "on"
cmp.w #1, AAF_select
jlo no_AAF ; unsigned
SetupADC10
call #SetupADC10_wakeup_AAF
jmp SetupOP0
no_AAF call #SetupADC10_wakeup_no_AAF
SetupOP0 call #SetupOP1_2
SetupTA_ call #SetupTA
call #INITMEM ; clear all variables
bis.w #MC_1, TACTL ; up mode, TA start
mov.b #LPM3+GIE, SR ; enable LPM3 mode and global interrupts
Mainloop jmp Mainloop
;------------------------------------------------------------------------------
TA0_ISR;
;------------------------------------------------------------------------------
bic.w #MC_1, TACTL ; TA stop
bis.b #BIT0, P4OUT ; microphone on
bis.b #BIT4, P2OUT ; offset on
bis.w #OAPM_3,&OA0CTL0_ ; start OP0 fast mode, amplifier
cmp.w #1, AAF_select
jlo cont_4 ; jump if no AAF selected
bis.w #OAPM_3,&OA1CTL0_ ; start OP1 fast mode, start filter
call #delay_8MHz_AAF ; OP settling time
jmp cont_5
cont_4 call #delay_8MHz_no_AAF ; OP settling time
cont_5 bis.w #ADC10ON,&ADC10CTL0
bis.w #ENC+ADC10SC,&ADC10CTL0 ; enable ADC10 + start conversion
wait_IFG bit.w #ADC10IFG, &ADC10CTL0 ; ADC10IFG set?
jz wait_IFG ; jump if ADC10IFG not set
bic.w #ADC10IFG, &ADC10CTL0
mov.w &ADC10MEM, temp1 ; save ADC10MEM to a working register
sub.w #520, temp1 ; subtract 520 because of 520 Offset
cmp.w #trigger_lvl_low, temp1 ; compare trigger level with input level
jl trigger ; temp1 < trigger level?
cmp.w #trigger_lvl_high, temp1; compare trigger level with input level
jge trigger ; temp1 > trigger level?
jmp no_trigger
trigger call #SetDCO_12Mhz
bic.w #ENC, &ADC10CTL0 ; disable ADC10
bit.w #BIT3, &OA1CTL0_
jz cont_9 ; jump if AAF off
call #SetupADC10_cont_AAF ; execute if AAF on
jmp cont_10
cont_9 call #SetupADC10_cont_no_AAF
cont_10 bis.w #ENC+ADC10SC,&ADC10CTL0 ; enable ADC10 + start conversion
bic.b #LPM3, 0(SP) ; disable LPM3 mode
reti
no_trigger
bic.w #OAPM0+OAPM1,&OA0CTL0_ ; OP0 off
bic.w #OAPM0+OAPM1,&OA1CTL0_ ; OP1 off
bic.w #ENC,&ADC10CTL0 ; disable ADC10
bic.w #ADC10ON, &ADC10CTL0 ; ADC10 off
bic.b #BIT0, P4OUT ; microphone off
bic.b #BIT4, P2OUT ; offset off
bis.w #MC_1, TACTL ; up mode, TA start
reti
;------------------------------------------------------------------------------
ADC10_ISR;
;------------------------------------------------------------------------------
mov.w &ADC10MEM, temp1 ; save ADC10MEM to a working register
sub.w #512, temp1 ; subtract 512 because of 512 Offset
inc sample_count
call #signal_analysis
reti
;------------------------------------------------------------------------------
signal_analysis; analysing input signal 60ms = 2336 samples at fs=38961Hz
;------------------------------------------------------------------------------
; begin averaging of input signal
clr res_avg
add.w temp1, res_avg
add.w avg_1, res_avg
add.w avg_2, res_avg
add.w avg_3, res_avg
mov.w avg_2, avg_3
mov.w avg_1, avg_2
mov.w temp1, avg_1 ; save active sample
rra.w res_avg ; divide result by 2
rra.w res_avg ; divide result by 2
; end averaging of input signal
; begin integration of samples
cmp.w #0, temp1
jl break_1 ; jump if temp1 < 0, signed
bic.w #C, SR
add.w temp1, integ_total
jnc break_1 ; jump if no overflow
inc.w div_count_1 ; count shift/div by 2 events
; end integration of samples
; begin peak count
break_1 cmp.w avg_temp_1, res_avg
jge break_2 ; jump if res_avg > avg_temp_1, signed
cmp.w avg_temp_1, avg_temp_2
jge break_2 ; jump if avg_temp_2 > avg_temp_1, signed
inc.w peaks
; end peak count
break_2 ; begin zero count
cmp.w #0, avg_temp_1
jl test_2 ; jump if avg_temp_1 < 0, signed
cmp.w #0, res_avg
jge break_3 ; jump if res_avg > 0, signed
jmp count
test_2 cmp.w #0, res_avg
jl break_3 ; jump if res_avg < 0, signed
count inc zeros
break_3 ; end zero count
mov.w avg_temp_1, avg_temp_2 ; save previous averaging results, avg_temp_2 holds result(n-2)
mov.w res_avg, avg_temp_1 ; save previous averaging results, avg_temp_1 holds result(n-1)
mov.w temp1, INPUT ; temp1 holds current sample
call #WDF
; begin integration of samples of WDF output
mov.w OUTP, temp1
test_1 cmp.w #0, temp1
jl break_4 ; jump if temp1 < 0
bic.w #C, SR
add.w temp1, integ_HPB
jnc break_4
inc.w div_count_2 ; count shift/div by 2 events
; end integration of samples of WDF output
break_4 ; begin ratio HP band/total band
cmp.w #2336, sample_count ; 2336 samples reached (60ms)?
jlo end_analyz ; if sample_count < 2336, unsigned
ADC_off bic.w #ENC+ADC10IE, &ADC10CTL0; disable ADC10
bic.w #OAPM0+OAPM1,&OA0CTL0_ ; OP0 amplifier off
bic.w #OAPM0+OAPM1,&OA1CTL0_ ; OP1 filter off
bic.b #BIT0, P4OUT ; mic off
bic.b #BIT4, P2OUT ; offset off
; begin pre-scaling
mov.w div_count_1, temp1
mov.w div_count_2, temp2
cmp.w temp2, temp1
jlo ratio_f_1 ; jump if div_count_1 < div_count_2
sub.w #0, temp1 ; begin shift values equal to their overflows
jz break_5 ; jump if div_count_1 = 0 -> if no overflow at integ_total occured
loop_1 cmp.w #1, temp2
jlo rrc_C_0 ; jump if div_count_2=0 and div_count_1!=0
bis.w #C, SR
rrc.w integ_HPB ; shifts integ_HPB through carry=1
dec.w temp2 ; decrement div_count_2 number once per shift operation
jmp cmp_temp1 ; finish div_count_2 test
rrc_C_0 bic.w #C, SR
rrc.w integ_HPB ; shifts integ_HPB through carry=0
cmp_temp1 bis.w #C, SR
rrc.w integ_total
dec.w temp1 ; sets carry while div_count_1!=0
cmp.w #1, temp1
jge loop_1 ; end shift values equal to their overflows
; end pre-scaling
break_5 ; begin division quotient=dividend/divisor
bit.w #8000, integ_HPB
jz cont_11 ; jump if integ_HPB(divisor) MSB="0"
bic.w #C, SR
rrc.w integ_HPB ; MSB="0" required
bic.w #C, SR
rrc.w integ_total ; shift to keep ratio konstant
cont_11 cmp.w #0,integ_HPB ; prevent division by zero
jeq ratio_f_1
mov.w integ_total, R15 ; R15 has dividend, R15 holds result
mov.w integ_HPB, R14 ; R14 has divisor
mov.w #16,R11 ; counter 16bit register = 16shifts
clr.w R13 ; A, R13 finaly holds the remainder
start rla.w R15 ; shift left by one
rlc.w R13 ; catches first bit of shiftet dividend
bis.w #1, R15 ; set last bit of dividend
sub.w R14,R13 ; A-divisor=A
jge loc1 ; A>=0 ?
add.w R14,R13
bic.w #1, R15 ; clear last bit depending on result of A-divisor=A
; A<0 bit one of dividend=1, A>0 bit one of dividend=0
loc1 dec.w R11
cmp.w #0,R11
jnz start
; end division quotient=dividend/divisor
; begin floating point of division
clr R12
rra R14 ; divider/4
rra R14
loop_2 sub.w R14, R13
cmp.w #0, R13
jl cont_test;
inc R12 ; counter, how often is divider/4 in remainder
cmp #3, R12 ; if more than 3 loops
jge cont_test
jmp loop_2
; end floating point of division
cont_test ; begin data interpretation
cmp.w #7, R15
jge ratio_f_1
cmp.w #1, R15
jl ratio_f_1
jne check_peaks
cmp #3, R12 ; check decimal point, 3=0.75
jl ratio_f_1
jmp check_peaks
check_peaks cmp.w #160, peaks
jlo peakfalse
cmp.w #320, peaks
jge peakfalse
check_zeros cmp.w #95, zeros
jlo zerofalse
cmp.w #300, zeros
jge zerofalse
jmp check
ratio_f_1 inc.w ratio_false ; set ratio false flag
jmp check_peaks
peakfalse inc.w peak_false ; set peak false flag
jmp check_zeros
zerofalse inc.w zero_false ; set zero crossing false flag
check cmp.w #1, ratio_false
jge break_6
cmp.w #1, peak_false
jge break_6
cmp.w #1, zero_false
jge break_6
; end data interpretation
glass_break bis.b #BIT0,&P1OUT ; set P1.0 = 1, turn led on
bis.b #BIT7,&P3OUT ; set P3.7 = 1, turn buzzer on
call #delay_12Mhz ; delay led/buzzer active time
bic.b #BIT0,&P1OUT ; set P1.0 = 0, turn led off
bic.b #BIT7,&P3OUT ; set P3.7 = 0, turn buzzer off
break_6 bit.w #BIT3, &OA1CTL0_
jz cont_7 ; jump if AAF off
call #SetupADC10_wakeup_AAF ; execute if AAF on
jmp cont_8
cont_7 call #SetupADC10_wakeup_no_AAF
call #INITMEM
cont_8 call #SetDCO_8Mhz
bis.w #MC_1, TACTL ; up mode, TA start
mov.b #LPM3+GIE, SR ; enable LPM3 mode and global interrupts
end_analyz ret
;-------------------------------------------------------------------------------
SetupADC10_wakeup_AAF; Setup ADC10 comparator
;-------------------------------------------------------------------------------
mov.w #ADC10SHT_1+ADC10SR, &ADC10CTL0
; 8 ADC10CLK S&H, max 50ksps
mov.w #INCH_13+ADC10DIV_2+ADC10SSEL_3+CONSEQ_0, &ADC10CTL1
; Channel A13, ADC10CLK=SMCLK/3
; Single Channel Conversion
ret
;-------------------------------------------------------------------------------
SetupADC10_wakeup_no_AAF; Setup ADC10 comparator
;-------------------------------------------------------------------------------
mov.w #ADC10SHT_1+ADC10SR, &ADC10CTL0
; 8 ADC10CLK S&H, max 50ksps
mov.w #INCH_1+ADC10DIV_2+ADC10SSEL_3+CONSEQ_0, &ADC10CTL1
; Channel A1, ADC10CLK=SMCLK/3
; Single Channel Conversion
ret
;-------------------------------------------------------------------------------
SetupADC10_cont_AAF; Setup ADC10 signal analysis
;-------------------------------------------------------------------------------
mov.w #ADC10SHT_3+ADC10SR+MSC+ADC10ON+ADC10IE, &ADC10CTL0
; Ref: VR+ = Vcc and VR- = Vss
; 64 ADC10CLK S&H, max 50ksps
; Multi S&C, ADC on, ADC IE
mov.w #INCH_13+ADC10DIV_3+ADC10SSEL_3+CONSEQ_2, &ADC10CTL1
; Channel A13, ADC10CLK=SMCLK/4
; Repeat Single Channel Conversion
ret
;-------------------------------------------------------------------------------
SetupADC10_cont_no_AAF; Setup ADC10 signal analysis
;-------------------------------------------------------------------------------
mov.w #ADC10SHT_3+ADC10SR+MSC+ADC10ON+ADC10IE, &ADC10CTL0
; Ref: VR+ = Vcc and VR- = Vss
; 64 ADC10CLK S&H, max 50ksps
; Multi S&C, ADC on, ADC IE
mov.w #INCH_1+ADC10DIV_3+ADC10SSEL_3+CONSEQ_2, &ADC10CTL1
; Channel A1, ADC10CLK=SMCLK/4
; Repeat Single Channel Conversion
ret
;-------------------------------------------------------------------------------
SetupOP1_2; Setup OP1 & OP2
;-------------------------------------------------------------------------------
OP0 mov.b #OAFBR_6+OAFC_6+OANEXT,&OA0CTL1_
; Inverting PGA, gain=-7
; inv input external available
mov.b #OAN_1+OAP_0+OAPM_0+OAADC1,&OA0CTL0_
; inv input OA0I1 P2.2
; non inv input OA0I0 P2.0
; off mode, OA0O at A13 & P2.1
OP1 mov.b #OAFC_2,&OA1CTL1_ ; Unity gain buffer
mov.b #OAP_3+OAPM_0+OAADC0,&OA1CTL0_
; non inv input OA1I1 P4.6
; off mode, OA1O at A13 & P4.4
bis.b #0f0h,&ADC10AE1 ; P4.4 OA1O, P4.6 OA1I3
ret
;-------------------------------------------------------------------------------
SetupTA; Setup TA wake up
;-------------------------------------------------------------------------------
mov.w #TASSEL0, TACTL ; TACLK=ACLK=VLO
mov.w #OUTMOD_4+CCIE, TACCTL0 ; toggle mode @ P1.1, CCRO IE
mov.w #TACCR0_2ms, TACCR0 ;
ret
;-------------------------------------------------------------------------------
SetDCO_12Mhz; Set DCO to 12Mhz and ACLK = VLO
;-------------------------------------------------------------------------------
mov.b &CALBC1_12MHZ,&BCSCTL1 ; set range
mov.b &CALDCO_12MHZ,&DCOCTL ; set DCO step + modulation
mov.b #LFXT1S_2, &BCSCTL3 ; ACLK = VLO
ret
;-------------------------------------------------------------------------------
SetDCO_8Mhz; Set DCO to 8Mhz and ACLK = VLO
;-------------------------------------------------------------------------------
mov.b &CALBC1_8MHZ,&BCSCTL1 ; set range
mov.b &CALDCO_8MHZ,&DCOCTL ; set DCO step + modulation
mov.b #LFXT1S_2, &BCSCTL3 ; ACLK = VLO
ret
;------------------------------------------------------------------------------
delay_12Mhz;
;------------------------------------------------------------------------------
clr R14
clr R13
incr_R13 inc.w R13
incr_R14 inc.w R14
cmp #12000, R14
jnz incr_R14
clr R14
cmp #1000, R13
jnz incr_R13
ret
;------------------------------------------------------------------------------
delay_8MHz_AAF;
;------------------------------------------------------------------------------
clr R14
clr R13
inc_R13 inc.w R13
inc_R14 inc.w R14
cmp #25, R14
jnz inc_R14
clr R14
cmp #1, R13
jnz inc_R13
ret
;------------------------------------------------------------------------------
delay_8MHz_no_AAF;
;------------------------------------------------------------------------------
clr R14
clr R13
inc_R13_ inc.w R13
inc_R14_ inc.w R14
cmp #1, R14
jnz inc_R14_
clr R14
cmp #1, R13
jnz inc_R13_
ret
;------------------------------------------------------------------------------
WDF; Bi-reciprocal WDF fs=38900
;------------------------------------------------------------------------------
// upper branch \\
; ** alpha 3 stage ** gamma=-0.375 -> Type 3, alpha=0.375
mov.w INPUT, inp13 ; WDF input
mov.w delay1, inp23
mov.w outp23, delay1
mov.w inp13, temp1
sub.w inp23, temp1
mov.w temp1, p13 ; p13=inp13-inp23
; begin shift & add multipication using horner method
clr.w temp2
sub.w temp1, temp2
mov.w temp2, temp1 ; negate temp1
rra.w temp1
rra.w temp1
add.w p13, temp1 ; 2
rra.w temp1 ; 1
; end shift & add multipication using horner method
mov.w temp1, temp2
sub.w inp13, temp2
mov.w temp2, outp23 ; outp23=temp1-inp13
sub.w inp23, temp1
mov.w temp1, outp13 ; outp13=temp1-inp23
; ** alpha 1 stage ** gamma=-0.109375 -> Type 3 alpha=0.109375
mov.w INPUT, inp11 ; WDF input
mov.w delay2, inp21
mov.w outp21, delay2
mov.w inp11, temp1
sub.w inp21, temp1
mov.w temp1, p11 ; p11=inp11-inp21
; begin shift & add multipication using horner method
clr.w temp2
sub.w temp1, temp2
mov.w temp2, temp1 ; negate temp1
rra.w temp1
rra.w temp1
rra.w temp1
add.w p11, temp1 ; 3
rra.w temp1
rra.w temp1
rra.w temp1
; end shift & add multipication using horner method
mov.w temp1, temp2
sub.w inp11, temp2
mov.w temp2, outp21 ; outp21=temp1-inp11
sub.w inp21, temp1
mov.w temp1, outp11 ; outp11=temp1-inp21
; ** alpha 5 stage ** gamma=-0.75 -> Type 4 alpha=0.75
mov.w outp11, inp15
mov.w delay3, inp25
mov.w outp25, delay3
mov.w inp25, temp1
sub.w inp15, temp1
mov.w temp1, p15 ; p15=inp25-inp15
; begin shift & add multipication using horner method
rra.w temp1
rra.w temp1
; end shift & add multipication using horner method
sub.w inp25, temp1
mov.w temp1, outp25 ; outp25=temp1-inp25
mov.w outp25, temp2
sub.w p15, temp2
mov.w temp2, outp15 ; outp15=outp25-p15
; begin final output
mov.w delay4, OUTP
sub.w outp15, OUTP ; high pass output
rra OUTP ; divide output by two
mov.w outp13, delay4
; end final output
ret
;-------------------------------------------------------------------------------
INITMEM; INIT Memory
;-------------------------------------------------------------------------------
clr.w INPUT
clr.w OUTP
clr.w inp11
clr.w inp21
clr.w outp11
clr.w outp21
clr.w inp13
clr.w inp23
clr.w outp13
clr.w outp23
clr.w inp15
clr.w inp25
clr.w outp15
clr.w outp25
clr.w delay1
clr.w delay2
clr.w delay3
clr.w delay4
clr.w temp1
clr.w temp2
clr.w avg_1
clr.w avg_2
clr.w avg_3
clr.w res_avg
clr.w avg_temp_1
clr.w avg_temp_2
clr.w peaks
clr.w zeros
clr.w integ_total
clr.w integ_HPB
clr.w sample_count
clr.w sample_count_2
clr.w div_count_1
clr.w div_count_2
clr.w ratio_false
clr.w peak_false
clr.w zero_false
ret
;------------------------------------------------------------------------------
COMMON INTVEC ; Interrupt Vectors
;------------------------------------------------------------------------------
ORG RESET_VECTOR ; MSP430 RESET Vector
DW RESET ;
ORG TIMERA0_VECTOR ; Timer_A0 Vector (CCRO IFG only)
DW TA0_ISR ;
ORG ADC10_VECTOR ; ADC10 Vector
DW ADC10_ISR ;
END
