#include <msp430g2553.h>
int PORT_count=0;
int PORT_INPUT;
int FLAG_PORT;
void Init_INPUT(void);
void Init_TIMERA(void);
void Delay_ms(unsigned long nValue);
void Delay_us(unsigned long nValue);
void main(void)
{
WDTCTL = WDTPW + WDTHOLD;
BCSCTL1=CALBC1_1MHZ;
DCOCTL=CALDCO_1MHZ;
BCSCTL2|= DIVS_3;
Init_INPUT();
Init_TIMERA();
}
void Init_INPUT(void)
{
P2SEL=0x00;
P2DIR |=BIT0+BIT1+BIT2+BIT3;
P2DIR &=~BIT4+~BIT5+~BIT6;
P2IE |=BIT4+BIT5+BIT6;
P2IES |=BIT4+BIT5+BIT6;
}
void Init_TIMERA(void)
{
TA1CTL =TASSEL1+ID_3+TACLR +MC1; //SMCLK,8 divide
TA1CCTL0 = CCIE;
TA1CCR0=15625; //time scan iternal 1s
}
#pragma vector=TIMER1_A0_VECTOR
__interrupt void ta0(void)
{
PORT_count+=1;
if(PORT_count==4)PORT_count=0;
switch(PORT_count)
{
case 0:
{
P2OUT&=~BIT0;
P2OUT|=BIT1+BIT2+BIT3;
break;
}
case 1:
{
P2OUT&=~BIT1;
P2OUT|=BIT0+BIT2+BIT3;
break;
}
case 2:
{
P2OUT&=~BIT2;
P2OUT|=BIT0+BIT1+BIT3;
break;
}
case 3:
{
P2OUT&=~BIT3;
P2OUT|=BIT0+BIT1+BIT2;
break;
}
default :break;
}
#pragma vector=PORT2_VECTOR
__interrupt void PORT_2(void)
{
Delay_us(100);
if(P2IFG&BIT4)
{
P2IFG&=~BIT4;
Delay_ms(1);
switch(PORT_count)
{
case 0: PORT_INPUT=1;
case 1: PORT_INPUT=4;
case 2: PORT_INPUT=7;
default :break;
}
FLAG_PORT=1;
}
if(P2IFG&BIT5)
{
P2IFG&=~BIT5;
Delay_ms(1);
switch(PORT_count)
{
case 0 : PORT_INPUT=2;
case 1 : PORT_INPUT=5;
case 2 : PORT_INPUT=8;
case 3 : PORT_INPUT=0;
default :break;
}
FLAG_PORT=1;
}
if(P2IFG&BIT6)
{
P2IFG&=~BIT6;
Delay_ms(1);
switch(PORT_count)
{
case 0: PORT_INPUT=3;
case 1:PORT_INPUT=6;
case 2:PORT_INPUT=9;
default :break;
}
FLAG_PORT=1;
}
}
void Delay_ms(unsigned long nValue)
{
unsigned long nCount;
int i;
unsigned long j;
nCount=5000;
for(i=nValue;i>0;i--)
{
for(j=nCount;j>0;j--);
}
}
void Delay_us(unsigned long nValue)
{
int nCount;
int i;
int j;
nCount=24;
for(i=nValue;i>0;i--)
{
for(j=aCount;j>0;j--);
}
}