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tlv320aic3104 I2S 使用问题

Other Parts Discussed in Thread: TLV320AIC3104

现象  使用STM32F104RE master tlv320aic3104 slave  ,参照datasheet配置完成后,再没有输入接入或者输入接地的情况下,I2S DOUT上有大量数据产生,正常输入波形信号也不能改变

问题1

MasterslaverI2S 硬件直连,未加电容电阻,是否会有影响

问题2

  出现这种问题的可能原因,是否ADC或者I2S配置有问题?

 

电路图如下:

Master

 

 

 

 

Slaver

 

软件配置如下:

//CLOCK

{0, 0x00},

{1, 0x80},

{102, 0x02},

{101, 0x00}, //PLLDIV OUT

{7, 0x0A},

{2, 0x00}, //NEED CHECK

{3, 0x81},  //P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

{8, 0x20}, //BCLK/WCLK is input

{4, 0x20},

{5, 0x1E},

{6, 0x00},

 

//I2S

{8, 0x20}, //BCLK/WCLK is input

{9, 0x07}, //I2S mode, 16bit //Check if re-sync need.

{10, 0x00},//OFFSET = 0

//output

{14, 0x00},// 鐢靛杈撳嚭

{40, 0xB0}, //1.8V

{42, 0x8E}, //  杈撳嚭绾т笂鍗囧欢鏃?400ms锛屼俊鍙蜂笂鍗囨椂闂?4ms}

 

//ADC

{19, 0x04}, // MIC1LP CONNECT TO LEFT-ADC, LEFT-ADC is powered up.

{24, 0x00}, // MIC1LP CONNECT TO RIGHT-ADC471

{22, 0x7C}, // RIGHT-ADC power up

{25, 0x40}, // MICBIAS power down //need check

{15, 0x28}, //Unmute Left PGA, set gain to 26 dB

{16, 0xFF}, //Unmute RIGHT PGA, set gain to 26 dB

 

//DAC

{37, 0xE0}, // Left DAC and RIGHT DAC is powered up. HPLCOM configured as independent single-ended output

{41, 0x01}, //LEFT volume follows RIGHT

{43, 0x09},

{44, 0x09},

{38, 0x10}, // HPRCOM configured as independent single-ended output

{51, 0x89},

{47, 0x89},

{58, 0x00},

{54, 0x80},

{65, 0x89},

{64, 0x80},

{72, 0x00},

{71, 0x80},

{7,  0x0A},

 

逻辑分析仪截图如下

 

 问题原文附件如下:tiv320aic3104 咨询.doc

  • 现象  使用STM32F104RE master tlv320aic3104 slave  ,参照datasheet配置完成后,再没有输入接入或者输入接地的情况下,I2S DOUT上有大量数据产生,正常输入波形信号也不能改变

    问题1

    MasterslaverI2S 硬件直连,未加电容电阻,是否会有影响

    问题2

      出现这种问题的可能原因,是否ADC或者I2S配置有问题?

     

    电路图如下:

    Master

     

     

     

     

    Slaver

     

    tlv320aic3104  配置如下:

    //CLOCK

    {0, 0x00},

    {1, 0x80},

    {102, 0x02},

    {101, 0x00}, //PLLDIV OUT

    {7, 0x0A},

    {2, 0x00}, //NEED CHECK

    {3, 0x81},  //P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

    {8, 0x20}, //BCLK/WCLK is input

    {4, 0x20},

    {5, 0x1E},

    {6, 0x00},

     

    //I2S

    {8, 0x20}, //BCLK/WCLK is input

    {9, 0x07}, //I2S mode, 16bit //Check if re-sync need.

    {10, 0x00},//OFFSET = 0

    //output

    {14, 0x00},// 鐢靛杈撳嚭

    {40, 0xB0}, //1.8V

    {42, 0x8E}, //  杈撳嚭绾т笂鍗囧欢鏃?400ms锛屼俊鍙蜂笂鍗囨椂闂?4ms}

     

    //ADC

    {19, 0x04}, // MIC1LP CONNECT TO LEFT-ADC, LEFT-ADC is powered up.

    {24, 0x00}, // MIC1LP CONNECT TO RIGHT-ADC471

    {22, 0x7C}, // RIGHT-ADC power up

    {25, 0x40}, // MICBIAS power down //need check

    {15, 0x28}, //Unmute Left PGA, set gain to 26 dB

    {16, 0xFF}, //Unmute RIGHT PGA, set gain to 26 dB

     

    //DAC

    {37, 0xE0}, // Left DAC and RIGHT DAC is powered up. HPLCOM configured as independent single-ended output

    {41, 0x01}, //LEFT volume follows RIGHT

    {43, 0x09},

    {44, 0x09},

    {38, 0x10}, // HPRCOM configured as independent single-ended output

    {51, 0x89},

    {47, 0x89},

    {58, 0x00},

    {54, 0x80},

    {65, 0x89},

    {64, 0x80},

    {72, 0x00},

    {71, 0x80},

    {7,  0x0A},

     

    逻辑分析仪截图如下

     

     

  • 现象  使用STM32F104RE master tlv320aic3104 slave  ,参照datasheet配置完成后,再没有输入接入或者输入接地的情况下,I2S DOUT上有大量数据产生,正常输入波形信号也不能改变

    问题1

    MasterslaverI2S 硬件直连,未加电容电阻,是否会有影响

    问题2

      出现这种问题的可能原因,是否ADC或者I2S配置有问题?

     

    电路图如下:

    Master

     

     

     

     

    Slaver

     

    软件配置如下:

    //CLOCK

    {0, 0x00},

    {1, 0x80},

    {102, 0x02},

    {101, 0x00}, //PLLDIV OUT

    {7, 0x0A},

    {2, 0x00}, //NEED CHECK

    {3, 0x81},  //P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

    {8, 0x20}, //BCLK/WCLK is input

    {4, 0x20},

    {5, 0x1E},

    {6, 0x00},

     

    //I2S

    {8, 0x20}, //BCLK/WCLK is input

    {9, 0x07}, //I2S mode, 16bit //Check if re-sync need.

    {10, 0x00},//OFFSET = 0

    //output

    {14, 0x00},// 鐢靛杈撳嚭

    {40, 0xB0}, //1.8V

    {42, 0x8E}, //  杈撳嚭绾т笂鍗囧欢鏃?400ms锛屼俊鍙蜂笂鍗囨椂闂?4ms}

     

    //ADC

    {19, 0x04}, // MIC1LP CONNECT TO LEFT-ADC, LEFT-ADC is powered up.

    {24, 0x00}, // MIC1LP CONNECT TO RIGHT-ADC471

    {22, 0x7C}, // RIGHT-ADC power up

    {25, 0x40}, // MICBIAS power down //need check

    {15, 0x28}, //Unmute Left PGA, set gain to 26 dB

    {16, 0xFF}, //Unmute RIGHT PGA, set gain to 26 dB

     

    //DAC

    {37, 0xE0}, // Left DAC and RIGHT DAC is powered up. HPLCOM configured as independent single-ended output

    {41, 0x01}, //LEFT volume follows RIGHT

    {43, 0x09},

    {44, 0x09},

    {38, 0x10}, // HPRCOM configured as independent single-ended output

    {51, 0x89},

    {47, 0x89},

    {58, 0x00},

    {54, 0x80},

    {65, 0x89},

    {64, 0x80},

    {72, 0x00},

    {71, 0x80},

    {7,  0x0A},

     

    逻辑分析仪截图如下

     

     

  • 主机的I2S 接口和AIC3104的I2S 接口电平一致的话,是可以直接连接的。
    没有输入或者输入接地的条件下,DOUT仍然有输出,应该是耦合进入噪声进去了,比如电源,layout等引入的噪声。
    您可以参考下这篇关于音频codec常见噪声问题的应用手册,分别从电源噪声,带外噪声,PLL噪声等几个常见的噪声源进行分析:
    www.ti.com/.../slaa749.pdf
    AIC3104部分的电路,建议参考EVM user's guide:
    www.ti.com/.../slau218a.pdf
  • 此问题不是噪声问题 ,是I2S数据不对,目前3104采用master模式数据OK,同时确实有噪声,但是采用slaver模式,数据采集都不对,完全只有噪声数据,暂时准备改用mater方案

    采用这种方案也遇到一个问题,在MCU端还没有发送任何数据的情况下,HPROUT是有声音输出的,为输入音乐,但是音量很小,有很大的噪声,这种可能是什么设置影响到的?

    在看到3104框图时候,发现有可能是因为SW-D1直连出去,但是找不到控制SW-D1到SW-D4的控制寄存器,请问它们如何控制?而且如果SW-D2和SW-D4闭合的时候,是否两个DAC都不可用?可否只闭合其中一个,另外一个DAC可用?