tlv320Ai32 噪声问题

bingjing mao

Prodigy 50 points

tlv320Ai32在输出音频时总有丝丝声，即使输出的滤波将噪声调整到90mV以下还是存在。测试发现HPout的噪声有将近480mV

请问这是什么原因，Ai32还有什么寄存器要设置的？

模拟电源的纹波大概60mV，有影响吗？

11 年多前

0 Flora Wang 11 年多前

TI__Expert 7710 points

你好：

可否简单描述下你的CLK配置？时钟来源，以及硬件的连接？

如果MCLK和I2S其他时钟不是同源，是会有输出音频时出现丝丝声的。

0 bingjing mao 11 年多前回复 Flora Wang

Prodigy 50 points

我们项目是用stm32的i2s连接tlv320ai32，mclk、BCLK、ws等均由stm32硬件产生

ai32配置如下

static u16 aic32config[AIC32_NUMREGS] = {
    // For: [FS=48 kHz][MCLK=12.0000 MHz]
    0x91, // 3 PLL A                           <- [PLL=ON][P=1][Q=2]
    0x20, // 4 PLL B                           <- [J=8]
    0xf0, // 5 PLL C                           <- [D=1920]
    0x00, // 6 PLL D                           <- [D=1920]
    0x0a, // 7 Codec Datapath Setup            <- [FS=48 kHz][LeftDAC=LEFT][RightDAC=RIGHT]

    0x04, // 8 Audio Serial Data A             <- [BCLK=Master][WCLK=Master][3DEffects=OFF][DigitalMIC=OFF]
    0x00, // 9 Audio Serial Data B             <- [Mode=I2S][Length=16-bit][TransferMode=Continous]
       0, // 10 Audio Serial Data C             <- [DataOffset=0]
     0x01, // 11 Audio Codec Overflow Flag       <- [ReadOnly]
       0x00, // 12 Audio Codec Digital Filter      <- [OFF]

RESERVED, // 13 <- [Reserved]
0x80, // 14 Headset Detection <- []

      0x02, // 15 Left ADC PGA Gain              <- [Mute=OFF]
     0x0, // 16 Right ADC PGA Gain              <- [Mute=OFF]
    0xff, // 17 MIC3L/R to Left ADC            <- [OFF]
    0xff, // 18 MIC3L/R to Right ADC            <- [OFF]
    0x24, // 19 LINE1L to Left ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
    0x78, // 20 LINE2L to Left ADC            <- [OFF]
    0x08, // 21 LINE1R to Left ADC            <- [OFF]
    0x0c, // 22 LINE1R to Right ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
    0x78, // 23 LINE2R to Right ADC            <- [OFF]
    0x80, // 24 LINE1L to Right ADC            <- [OFF]
       0x80, // 25 MICBIAS                         <- [Power=OFF]

      0x00, // 26 Left AGC A                     <- [LeftAGC=OFF]
       0x0, // 27 Left AGC B                     <- [OFF]
       0xc3, // 28 Left AGC C                     <- [OFF]
      0x00, // 29 Right AGC A                     <- [RightAGC=OFF]
       0x0, // 30 Right AGC B                     <- [OFF]
       0x0, // 31 Right AGC C                     <- [OFF]
READONLY, // 32 Left AGC Gain                  <- [ReadOnly]
READONLY, // 33 Right AGC Gain                  <- [ReadOnly]
       0x0, // 34 Left AGC Noise Debounce        <- []
       0x0, // 35 Right AGC Noise Debounce        <- []
READONLY, // 36 ADC Flag                        <- [ReadOnly]

    0xe0, // 37 DAC Power & Output Dvr          <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd]
    0x10, // 38 High Power Output Dvr           <- [HPRCOM=SingleEnd][ShortCircuit=OFF]
RESERVED, // 39                                 <- [Reserved]
       0x00, // 40 High Power Output Stage         <- []
       0x0d, // 41 DAC Output Switching            <- []
       0, // 42 Output Driver Pop Reduction     <- []

0x0, // 43 Left DAC Digital Volume <- [Mute=OFF][Gain=0dB]
0x0, // 44 Right DAC Digital Volume <- [Mute=OFF][Gain=0dB]

       0, // 45 Line2L to HPLOUT Volume         <- []
      0x14, // 46 PGA_L to HPLOUT Volume         <- []
      0x90, // 47 DAC_L1 to HPLOUT Volume         <- []
       0, // 48 LINE2R to HPLOUT Volume         <- []
       0x0, // 49 PGA_R to HPLOUT Volume         <- []
      0x0, // 50 DAC_R1 to HPLOUT Volume         <- []
      0x99, // 51           HPLOUT Output         <- []

       0, // 52 LINE2L to HPLCOM Volume         <- []
       0, // 53 PGA_L to HPLCOM Volume         <- []
       0, // 54 DAC_L1 to HPLCOM Volume         <- []
       0, // 55 LINE2R to HPLCOM Volume         <- []
       0, // 56 PGA_R to HPLCOM Volume         <- []
       0, // 57 DAC_R1 to HPLCOM Volume         <- []
       0, // 58           HPLCOM Output         <- []

       0, // 59 LINE2L to HPROUT Volume         <- []
       0x0, // 60 PGA_L to HPROUT Volume         <- []
       0x0, // 61 DAC_L1 to HPROUT Volume         <- []
       0, // 62 LINE2R to HPROUT Volume         <- []
       0x0, // 63 PGA_R to HPROUT Volume         <- []
       0x80, // 64 DAC_R1 to HPROUT Volume         <- []
       0x99, // 65           HPROUT Output         <- []
};