RE: TLV320ADC5140: TLV320ADC5140 Unable to capture sound

Hi,

Thanks for confirming, this is a supported settting as per the table in datasheet.

said:

Register address: ASI_STS , register status: ff
Register address: DEV_STS0 , register status: 0
Register address: DEV_STS1 , register status: c0

Assuming that these registers were read back while the recording is in progress, as mentioned above, device is indicating an invalid BCLK and FSYNC input.

1) Is it possible to confirm the BCLK and FSYNC inputs to the device are as expected using oscilloscope?

2) Can we also update these two register configurations?

ADC_DATE_INPUT(0x16 , 0x08) - this was written as 0x88, which makes the ADC clock source as MCLK in master mode with PLL disabled case. Since the PLL is enabled in this configuration, we can use the BCLK as source clock.

 ADC_DATE_INPUT(0x1F , 0x41); //Reserved field is being overwritten when making this 0x01, default value is 0x40

Thanks and Regards,

Lakshmi Narasimhan