Part Number: TLV320AIC23
使用该器件采集6KHz正弦波,配置MCLK二分频得到16KHz采样率,使用I2S格式传输数据,BCLK为512K,也尝试过配置为1/4的MCLK
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Part Number: TLV320AIC23
使用该器件采集6KHz正弦波,配置MCLK二分频得到16KHz采样率,使用I2S格式传输数据,BCLK为512K,也尝试过配置为1/4的MCLK
{0x36, 0x0f, 0x000},//reset first {0x36, 0x00, 0x017}, {0x36, 0x01, 0x017}, {0x36, 0x02, 0x0FF}, {0x36, 0x03, 0x0FF}, {0x36, 0x04, 0x012},//0x018 {0x36, 0x05, 0x006}, {0x36, 0x06, 0x00A},//0X00A {0x36, 0x07, 0x002},//0x00A {0x36, 0x09, 0x001}, {0x36, 0x08, 0x098},//0x018 ==32k0x098==16k0x008==8k0
第二列是寄存器,第三列是配置字,MCLK采用12.288MHz,AIC23作I2S的slave,FPGA作master,BCLK采用2*fs*bits,我们是16KHz采样率,16位数据,所以BCLK是512KHz。
你好,
你能提供你正在使用的MCLK、BCLK和WCLK吗?为了我的理解,我已经注释了你的登记簿,我也会把它放在这里。如果你能在测量失真和频率折叠时提供示波器(信号和时钟)的屏幕截图或图片,那也很好。
{0x36, 0x0f, 0x000},//reset first {0x36, 0x00, 0x017}, #left line input channel volume, default value 0dB {0x36, 0x01, 0x017}, #right line in {0x36, 0x02, 0x0FF}, #left headphone volume control simultaneous update l/r, volume=+6dB {0x36, 0x03, 0x0FF}, #same for r headphone {0x36, 0x04, 0x012},//0x018 #0x12->sidetown disabled, dac selectd, bypass disabled, line in for adc, mic mute=muted, micboost=0dB {0x36, 0x05, 0x006}, #dac soft mute disabled, 48khz deemphasis control, adc hpc enabled {0x36, 0x06, 0x00A},//0X00A #device power=on,clock on, oscillator on, outputs on, line input on, mic input off, adc off, dac on {0x36, 0x07, 0x002},//0x00A #0x02->i2s mode, msb first, 16 bit, slave mode {0x36, 0x09, 0x001}, #activate interface {0x36, 0x08, 0x098},//0x018 ==32k0x098==16k0x008==8k0 #clkout=mclk/2, clkin=mclk, sr[3:0]=0110, bosr=256fs, clock mode=normal (not usb) # sample rate=32kHz for mclk=12.288 or 18.432MHz