Dear experts
I used a CDCLVD1204 as a clock fan out, and the schematic diagram is shown below. The input of channel 0 is provided by a crystal oscillator, while channel 1 is an external input. SEL control is controlled by FPGA. When channel 0 is selected as the input, CDCLVD1204 outputs normally. However, when SEL is controlled to a high level and channel 1 is selected as the input, CDCLVD1204 does not output. R128, R129, R132, and R133 are not soldered, and the VACREF pin output voltage is not 1.25V but 1.8V. R106 has been replaced with a 0 ohm resistor. What is the design problem of this circuit? Why is there no output when channel 1 is selected as the input of CDCLVD1204? We have ensured that the common mode voltage and VPP of the IN1 clock meet the requirements of the chip manual
Thank you for your answer
