• 状态 Resolved
  • 回复 7 回复
  • 订户 8 订户
  • 视图 168 视图
  • 用户 0 会员在此处
选项
选项
相关

LMX2595: Dual-lock phase-locked loop frequency source design

Z RX
Prodigy 20 points
Part Number: LMX2595
Other Parts Discussed in Thread: LMX2581, LMX2541, LMX2485E, LMX2485, LMX2485Q-Q1, OPA211

Dear TI Technical Support Team,

I am designing a wideband RF signal source covering the full range of the LMX2595. My primary design challenge is minimizing close-in fractional spurs across the entire tuning range. I am evaluating a cascaded dual-LMX2595 architecture to address this.

Proposed Strategy (Tunable Reference): I intend to use a "Smart Reference" approach:

  1. 1st Stage LMX2595 (Fractional / Fine Tune): Acts as a variable reference source. It operates in Fractional Mode, generating a tunable output (e.g., varying between 80 MHz and 150 MHz).

  2. 2nd Stage LMX2595 (Integer / Multiplier): Acts as the main LO. Ideally, this stage operates in Integer Mode (or optimal fractional mode) to avoid generating its own close-in spurs.

  3. Concept: To tune the final output, I will adjust the 1st stage frequency so that the 2nd stage can maintain an Integer-N relationship (or optimal PFD ratio) with the target output frequency.

Questions:

  1. Feasibility: Is this "Tunable Reference" cascaded architecture recommended for wideband applications where the output is not fixed?

  2. Filtering Challenge: Since the interface frequency between Stage 1 and Stage 2 is variable, I cannot use a fixed narrowband filter (like a SAW or Crystal). Would a simple Low Pass Filter (LPF) combined with a very narrow Loop Bandwidth (< 10 kHz) on the 2nd stage be sufficient to suppress the fractional spurs generated by the 1st stage?

  3. Spur Propagation: Since the 2nd stage acts as a high-gain multiplier (20logN), any spur from the 1st stage is amplified. Does TI have any recommendations or frequency planning algorithms (possibly within TICS Pro) to calculate optimal "Reference vs. N-Divider" combinations? The goal is to push the 1st stage spurs far enough out so they are attenuated by the 2nd stage's loop filter.

  4. Alternatives: For wideband low-spur requirements, is there a better configuration than cascading two devices? (e.g., Using the onboard Multiplier with dynamic PFD shifting on a single chip).

Thank you for your guidance.

Best regards,
RX

  • 0
    TI__Mastermind 43185 points

    您好

    已经收到了您的案例，调查需要些时间，感谢您的耐心等待

  • 0 回复 Daniel
    TI__Mastermind 32315 points

    We need narrow loop bandwidth to reduce spurs from the first stage. If we use LMX2595 as the first stage, output phase noise is pretty much equal to the VCO phase noise, which is not good enough to be used as the reference clock to the second stage. We need a PLL + good phase noise VCO to build the first stage. LMX2481E is able to support 80M to 100MHz VCO. 

  • 0 回复 Eirwen
    Prodigy 20 points

    Hi Eirwen,

    Thank you for the valuable feedback regarding the narrow loop bandwidth architecture. I agree that using a clean reference for the second stage is critical.

    Regarding your suggestion to replace the first stage LMX2595, I have two follow-up questions:

    1. Part Number Clarification (LMX2481E vs LMX2581)

    I searched for the "LMX2481E" you mentioned but could not find a product page for it on TI.com.

    • Did you mean the [LMX2581]?

    • Or are you referring to a different device (perhaps the LMX2485E external PLL or LMX2541)?

      I noticed the LMX2581 is available and covers the frequency range, so I am assuming this might be the intended part.

    2. VCO Phase Noise Comparison

    I compared the datasheet specifications for the LMX2595 and LMX2581 (assuming this is the correct comparison), and I am trying to understand the performance gap you mentioned.

    • LMX2595 (VCO1): -107 dBc/Hz @ 100 kHz offset (f_vco = 8 GHz).

    • LMX2581 (Core 1): -114.5 dBc/Hz @ 100 kHz offset (f_vco = 1.9 GHz).

    At first glance, the raw numbers look similar (approx. 7dB difference). However, if I theoretically normalize the LMX2595's 8 GHz VCO down to 1.9 GHz using a divider ($20\log(N)$ improvement), the LMX2595 actually seems to have a theoretical noise floor comparable to or even lower than the LMX2581.

    Could you please elaborate on why the LMX2581 (or the specific part you recommended) is superior in this specific "Smart Reference" application? Is it related to the 1/f noise corner, the noise floor at the specific 80-100MHz output, or the spurious performance rather than just phase noise?

    Thank you for your guidance.

    Best regards,

    RX

  • +1 回复 Z RX
    TI__Mastermind 32315 points

    I am sorry, there was a typo, the PLL is LMX2485E. 

    I suggest use discrete PLL + VCO with a narrow loop bandwidth filter for the first stage, this will ensure we have low spurs and good phase noise.

  • 0 回复 Eirwen
    Prodigy 20 points

    Hi Eirwen,

    Thanks for the clarification. The LMX2485E recommendation makes perfect sense now.

    1. Regarding the LMX2485 Family: I have actually looked into the LMX2485Q-Q1 previously and am aware of its excellent performance in Fractional-N mode, particularly its higher order Delta-Sigma modulator which helps in spur management. It seems like a solid choice for the first stage.

    2. Discrete PLL + VCO Implementation: Since my previous designs mainly relied on fully integrated synthesizers (like the LMX2595), this will be my first time implementing a discrete PLL (LMX2485E) driving an external VCO.

      Could you share any "best practices" or common pitfalls I should watch out for during the schematic and layout design?

      • Specifically: Are there critical considerations regarding the RF Interface matching between the VCO output and the PLL's feedback input (Fin)?

      • Charge Pump / Loop Filter: Are there special requirements for the active loop filter topology when driving a wideband external VCO?

      Any application notes or reference designs for this specific "LMX2485 + External VCO" pairing would be greatly appreciated.

    Best regards,

    RX

  • +1 回复 Z RX
    TI__Mastermind 32315 points

    The matching between VCO and PLL is not important, as long as there is sufficient signal going back to the PLL, it is fine.

    If you are planning to use active loop filter, depending on your amplifier configuration, you may need to change the phase detector polarity, which is configurable. Low noise op-amp such as OPA211 is recommended. 

    You can use PLL Sim (www.ti.com/.../PLLATINUMSIM-SW) to design the loop filter, active filter type B is my preference configuration as it requires less component.

    FYI, attached is the user's guide for one of the EVMs using active filter. However, we do not support EVM for this device anymore.

    LMX2485activeEVK.pdf

  • 0 回复 Eirwen
    Prodigy 20 points

    Hi Eirwen,

    Thank you so much for the detailed guidance! This clears up all my concerns regarding the discrete PLL implementation.

    I now have a clear path forward for the first stage design. Thank you again for your excellent support!

    Best regards,

    RX