
您好!按图示供电后,在输入20Mhz的CLK input时,VDDOUT从3.3V掉到0V,这种情况应该怎么查问题呢?
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您测试了几块电路板是这种情况?
VDD和VDDout 供电电压是否在正常范围内?您输入的时钟高电平和低电平分别是多少?
您可以附上产生1.8V LVCMOS时钟芯片和CDCE813R02-Q1的电路图吗?
Vctr管脚是VXCO的控制电压,默认情况下是LVCMOS时钟输入,那么就不需要Vctr管脚,可以悬空Vctr管脚,您将Vctr管脚悬空看是否解决问题?
不配置的时候IIC可以悬空;