Other Parts Discussed in Thread: TIDA-01410, LMX2486
各位TI专家，我在看这个文档：
TIDA-01410 （tidud11.pdf)
Phase Synchronization of Multiple PLL Synthesizers Reference Design
第2.2.1节“相位同步理论”中，有这样一段话：
For instance, whenever a signal is divide-by-two there are two possible output
phases, which requires the designer to take action. If this divider is inside the PLL feedback loop (PLL_N),
then the correct phase is always found by the PLL loop itself and no synchronization is required. However,
if this divider is outside the loop, such as in the case of using the input divider (PLL_R), then the designer
must provide a synchronization signal. This scenario also applies to the divider after the VCO (CHDIV).
Synchronization may also be required when fractional circuitry is involved.
我不明白“信号二分频后有两个可能的输出相位”是什么意思，在PLL控制中有什么具体影响，能否给解释一下？
是不是可以类推，3分频会有3种可能相位输出，4分频会有4种，等等。但是分频后每个上升沿都跟原信号的上升沿是对齐的，应该不影响同步吧？
