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AMC131M03-Q1: Offset Calibration

Part Number: AMC131M03-Q1

When performing offset calibration for the AMC131M03-Q1 using internal registers, since each chip exhibits different offset voltages, the register values written to different chips should theoretically vary. However, the customer expects a unified calibration value that can limit the deviation within 5 μV.

Question 1:
Would it be feasible to obtain a unified calibration value by testing the offset voltages of multiple chips, deriving a normal distribution of these offsets, and then using the mean (expected value) of this distribution as the unified calibration value?

Question 2:
If feasible, how many chips should be tested for statistical distribution analysis to ensure reliability?

Question 3:
If not feasible, do you recommend any alternative solutions to achieve a unified calibration value?

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  • The typical value listed in the datasheet is based on a statistical distribution of device offset measurements post-trim in production.

    Ideally the customer would do an end of line calibration, but they can try the following:

    1. Using Global-Chop Mode - This should cancel out the device offset in the measurements by periodically switching the input polarity.
    2. Doing an offset calibration in the field during system startup and/or periodically while the system is running