ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL: AMC1306M25

You can't just take 16-bits of data from the modulator and call it a day.  All streams are valid and their filtered results reflect whatever is applied to the inputs.  I'll try to find an app note or two that points out the high level detail of the inner working of a Delta Sigma Filter Module, but right now I can't think of any that go down to the bit-stream level. 

You need to apply a digital filter to the output bit-stream in order to recover the original analog input waveform.  That involves an over-sampling ratio and averaging the density of one's and zeros coming from the modulator.  The decimation is what provides the 16-bit result, not just some random collection of this or that 16-bit stream.

Yes - a digital filter can be implemented in an FPGA, please refer to the code we published for the ADS1202 a while back.