Part Number: DAC8734
Other Parts Discussed in Thread: REF6225
I'm designing a mixed-signal PCB that will include multiple ADCs and DACs (e.g., DAC8734) along with digital control circuitry (MCU/FPGA). My goal is to minimize the impact of digital noise on the analog performance. I have several questions regarding the overall layout strategy:
1. Partitioning: How should I physically partition the board between analog and digital sections? Should ADCs/DACs be placed at the boundary between the two regions, with their analog pins facing the analog section and digital pins facing the digital section? What minimum separation distance is recommended between analog and digital areas?
2. Grounding strategy: TI's documentation presents two common grounding approaches: (a) a single, solid ground plane; (b) split analog and digital ground planes with single-point connection. Which approach is recommended for a board with multiple ADCs and DACs? I've seen that for multiple converters, the analog and digital ground planes should be connected together solidly under all ADC/DAC chips, with each ground plane connected individually back to the power supply. Could you elaborate on how to implement this correctly?
3. Power supply routing: How should power be distributed to minimize noise coupling? Should power enter the board at the digital partition first, then be filtered/regulated to supply the analog section? Should separate LDOs be used for analog and digital supplies, and how should the ground returns for these supplies be handled?
4. Digital signal routing: When digital control signals (e.g., SPI, parallel bus from MCU/FPGA to ADCs/DACs) must travel across the board, how should they be routed to avoid coupling into analog circuits? What is the proper way to handle return currents for these signals?
5. Reference voltage layout: In a system where a single reference (e.g., REF6225) drives multiple ADCs and DACs, what are the layout recommendations to maintain reference accuracy and minimize ripple coupling?
6. Bypassing and decoupling: What are the best practices for placing bypass capacitors for multiple data converters? Should capacitors be placed on the same layer as the device, with vias not placed between the capacitor and the device pins?
7. Reference documents: Could you point me to any TI application notes, reference designs, or E2E threads that specifically address multi-converter mixed-signal layout (especially involving both ADCs and DACs together)? I've already reviewed the FAQ on high-resolution ADC layout, but would like more detailed guidance for systems with multiple converters.
Thank you for your guidance!
