ADS127L14: Issue of 4‑channel parallel data output for ADS127L14 under 32.768 MHz clock

Hello, I have revised my PCB design. The RESET, START, MODE, TDM and HDR pins are now brought out and controlled by the MCU via an independent ISO6760 isolator. In addition, the CAPA filter capacitor is changed to 10 µF and CAPD to 2.2 µF. Currently, the DCLN clock and FSYNK signals can be triggered successfully.

However, I have an issue: I need to synchronously acquire sensor data from 4 channels at a sampling rate of 515 kSPS with 24‑bit data precision, using an external 32.768 MHz clock. I configured the relevant registers via SPI, including selecting the external crystal oscillator, setting 24‑bit data format, ADC clock divider = 1, DOUT output divider = 2 (16.384 MHz), DP_TDM[1:0] = 3, and DP_DAISY = 1.

After these configurations, logic analyzer measurements show that there are only 16 clock cycles within one single FSYNK period instead of 24. Moreover, even when I set the DOUT divider to 1 via SPI, the output clock frequency remains constant at 16.7 MHz. What causes this problem?

Additionally, how should I configure the chip to achieve parallel sampling and parallel output for the 4 channels? Specifically, 4‑channel data should be output in parallel through DOUT0~3 under a single clock signal.