Part Number: DAC38J82Other Parts Discussed in Thread: LMK04828, LMK04821
DAC38J82: DAC38J82 FIFO errors: read_empty : FIFO is empty
Hello, we have received your case and the investigation will take some time. Thank you for your patience.
Hello,
Generally, "read FIFO empty" error is related with either the sample clock or SYSREF not at the correct frequency.
Similar issue discussed for you reference.
DAC38J82: DAC gives an error - read_empty : FIFO is empty - Data converters forum - Data converters - TI E2E support forums
Hi Alice,
The DAC and FPGA are clocked using the LMK04828.
DAC clock = 1200M , sysref = 18.75M
FPGA clock = 150M , sysref = 18.75M
DAC Configuration: LMFS=8212, HD=1, K=32, interp=1x , subclass 1, link0 is used.
the LMK04828 Configuration:
Could you help check this case? Thanks.
Best Regards,
bob
0x000080 # 001 , 0x000000 # 002 , 0x000200 # 003 , 0x000306 # 004 , 0x0004D0 # 005 , 0x00055B # 006 , 0x000600 # 007 , 0x000C51 # 008 , 0x000D04 # 009 , 0x010003 # 010 , DCLKout0_DIV0x010155 # 011 , 0x010300 # 012 , DCLKout0_MUX=Divider only0x010402 # 013 , SDCLKout1_MUX=Device clock , SDCLKout1_DDLY0x010500 # 014 , 0x010679 # 015 , CLKout0_1_PD , SDCLKout1_PD0x010700 # 016 , SDCLKout1_FMT , DCLKout0_FMT 0x010803 # 017 , DCLKout2_DIV0x010955 # 018 , 0x010B00 # 019 , DCLKout2_MUX=Divider only0x010C02 # 020 , SDCLKout3_MUX=Device clock , SDCLKout3_DDLY0x010D00 # 021 , 0x010E79 # 022 , CLKout2_3_PD , SDCLKout2_PD0x010F00 # 023 , SDCLKout3_FMT , DCLKout2_FMT 0x011008 # 024 , DCLKout4_DIV0x011155 # 025 , 0x011300 # 026 , DCLKout4_MUX=Divider only0x011402 # 027 , SDCLKout5_MUX=Device clock , SDCLKout5_DDLY0x011500 # 028 , 0x011679 # 029 , CLKout4_5_PD , SDCLKout4_PD0x011700 # 030 , SDCLKout5_FMT , DCLKout4_FMT 0x011802 # 031 , CLKoutX_Y_ODL=0 , CLKoutX_Y_IDL=0 , DCLKout6_DIV=20x011955 # 032 , 0x011B00 # 033 , DCLKout6_MUX=Divider only0x011C22 # 034 , SDCLKout7_MUX=SYSREF , SDCLKout7_DDLY0x011D00 # 035 , # 0x011EF1 # 036 , CLKout6_7_PD , SDCLKout7_PD0x011EF0 # 036 , CLKout6_7_PD , SDCLKout7_PD0x011F55 # 037 , SDCLKout6_FMT , DCLKout7_FMT # 0x012018 # 038 , DCLKout8_DIV=24# 0x01200C # 038 , DCLKout8_DIV=120x012010 # 038 , DCLKout8_DIV=160x012155 # 039 , 0x012300 # 040 , DCLKout8_MUX=Divider only0x012422 # 041 , SDCLKout9_MUX=SYSREF , SDCLKout9_DDLY0x012500 # 042 , # 0x0126F1 # 043 , CLKout8_9_PD , SDCLKout9_PD=10x0126F0 # 043 , CLKout8_9_PD , SDCLKout9_PD=00x012711 # 044 , SDCLKout9_FMT , DCLKout8_FMT # 0x012818 # 045 , DCLKout10_DIV=24# 0x012814 # 045 , DCLKout10_DIV=200x012810 # 045 , DCLKout10_DIV=160x012955 # 046 , 0x012B00 # 047 , DCLKout10_MUX=Divider only0x012C22 # 048 , SDCLKout11_MUX=SYSREF , SDCLKout11_DDLY0x012D00 # 049 , 0x012EF1 # 050 , CLKout10_11_PD , SDCLKout11_PD0x012F11 # 051 , SDCLKout11_FMT , DCLKout10_FMT 0x013006 # 052 , DCLKout12_DIV0x013155 # 053 , 0x013300 # 054 , DCLKout12_MUX=Divider only0x013402 # 055 , SDCLKout13_MUX=Device clock , SDCLKout13_DDLY0x013500 # 056 , 0x013679 # 057 , CLKout12_13_PD , SDCLKout13_PD0x013700 # 058 , SDCLKout13_FMT , DCLKout12_FMT 0x013800 # 059 , VCO_MUX=VCO_0 , OSCout_FMT=Powerdown0x013903 # 060 , SYSREF_MUX=SYSREF continuous# 0x013902 # 060 , SYSREF_MUX=SYSREF pulser0x013A00 # 061 , SYSREF_DIV[12:8] , SYSREF_DIV=1280x013B80 # 062 , SYSREF_DIV[7:0] ,# 0x013A01 # 061 , SYSREF_DIV[12:8] , SYSREF_DIV=256# 0x013B00 # 062 , SYSREF_DIV[7:0] ,0x013C00 # 063 , SYSREF_DDLY[12:8]0x013D08 # 064 , SYSREF_DDLY[7:0]0x013E03 # 065 , SYSREF_PULSE_CNT=8 pulses=30x013F06 # 066 , PLL1_NCLK_MUX=OSCin , FB_MUX=External 0x014083 # 067 , PLL1_PD=1 , VCO_LDO_PD=0 , VCO_PD=0 , OSCin_PD=0 , SYSREF_GBL_PD=0 , SYSREF_PD=0 , SYSREF_DDLY_PD=1 , SYSREF_PLSR_PD=1# 0x014082 # 067 , PLL1_PD=1 , VCO_LDO_PD=0 , VCO_PD=0 , OSCin_PD=0 , SYSREF_GBL_PD=0 , SYSREF_PD=0 , SYSREF_DDLY_PD=1 , SYSREF_PLSR_PD=00x014100 # 068 , 0x014200 # 069 , # 0x014311 # 070 , SYSREF_CLR , SYNC_1SHOT_EN , SYNC_POL , SYNC_EN=1 , SYNC_PLL2_DLD , SYNC_PLL1_DLD , SYNC_MODE=10x014312 # 070 , SYSREF_CLR , SYNC_1SHOT_EN , SYNC_POL , SYNC_EN=1 , SYNC_PLL2_DLD , SYNC_PLL1_DLD , SYNC_MODE=2# 0x014352 # 070 , SYSREF_CLR , SYNC_1SHOT_EN=1 , SYNC_POL , SYNC_EN=1 , SYNC_PLL2_DLD , SYNC_PLL1_DLD , SYNC_MODE=20x0144FF # 071 , SYNC_DISSYSREF=1 , SYNC_DIS12 , SYNC_DIS10 , SYNC_DIS8 , SYNC_DIS6 , SYNC_DIS4 , SYNC_DIS2 , SYNC_DIS00x01457F # 072 , 0x145 = 127 (0x7F)0x014600 # 073 , 0x01470F # 074 , 0x01480B # 075 , 0x01494B # 076 , 0x014A02 # 077 , 0x014B02 # 078 , 0x014C00 # 079 , 0x014D00 # 080 , 0x014EC0 # 081 , 0x014F7F # 082 , 0x015003 # 083 , 0x015102 # 084 , HOLDOVER_DLD_CNT0x015200 # 085 , HOLDOVER_DLD_CNT 0x015300 # 086 , CLKin0_R0x015478 # 087 , CLKin0_R0x015500 # 088 , CLKin1_R0x015678 # 089 , CLKin1_R0x015700 # 090 , CLKin2_R0x015893 # 091 , CLKin2_R0x015900 # 092 , PLL1_N0x015A3C # 093 , PLL1_N0x015BD4 # 094 , 0x015C20 # 095 , 0x015D00 # 096 , 0x015E00 # 097 , 0x015F0B # 098 , 0x016000 # 099 , 0x016101 # 100 , 0x016245 # 101 , PLL2_P=2=010 , OSCin_FREQ=63-127M=001 , PLL2_XTAL_EN=amplifier disabled=0 , PLL2_REF_2X_EN=10x016300 # 102 , PLL2_N_CAL0x016400 # 103 , PLL2_N_CAL0x01650C # 104 , PLL2_N_CAL0x0171AA # 105 , 0x017202 # 106 , Program registers 0x17C and 0x17D as required by OPT_REG_1 and OPT_REG_20x017300 # 107 , PLL2_PRE_PD = 0 , PLL2_PD = 00x017400 # 108 , If using LMK04821, program register 0x174.0x017C15 # 109 , OPT_REG_10x017D33 # 110 , OPT_REG_20x016600 # 111 , PLL2_N0x016700 # 112 , PLL2_N0x016806 # 113 , PLL2_N=60x016959 # 114 , 0x016A20 # 115 , 0x016B00 # 116 , 0x016C00 # 117 , PLL2_LF_R40x016D00 # 118 , PLL2_LF_C40x016E13 # 119 , PLL2_LD_MUX , PLL2_LD_TYPE0x1FFD00 # 120 , 0x1FFE00 # 121 , 0x1FFF53 # 122 ,
