ADC09QJ1300-Q1: 激光雷达EMC测试问题ADC09QJ1300-Q1

Part Number: ADC09QJ1300-Q1

1,产品EMC测试中测试RE1.562G超标,直接使用频谱仪探测单板,发现LMK05318BTRGZTQ1时钟芯片正上方探测到26dB的1.562G的辐射,其他位置时钟供给ADC和FPGA的时钟走线外层附件可以探测到约15dB的1.562G的辐射,目前结构做屏蔽罩罩住时钟芯片有点困难,麻烦看下有没有什么处理手段

2,ADC芯片是否支持展频的时钟输入。

3,我们目前时钟输入Dclk是156.25M,sysref_p是4.8828M,采样率是1.25G,四通道jmode10 ,FPGA使用156.25M时钟接收数据,测试数据和原理图等见附件

4,我们想避开1.5G-1.6G的频段应该怎么设置,我们设置Dclk为125M,N从8变成10,其他设置不变,FPGA无法读取数据,ADC寄存器:

设置125M N=10时,测试TRIGOUT为488M,读取JESD_STATUS Register (Address = 0x208) [reset = 0x0] 值为0xC0 

设置156.25M N=8时,测试TRIGOUT为488M,读取JESD_STATUS Register (Address = 0x208) [reset = 0x0] 值为0x00

使用Xilinx的IP核读取,申请的TI204C-IP一直没有后续。


const u32 adc_config[] = {
                0x00B0,
                0x0200,
                0x1000,
                0x29E0,
                0x2A00,
                0x2B15,
                0x30FF,
                0x31FF,
                0x374B,
                0x3B00,
                0x3C01,
                0x3D06,
                0x3e0a, //0x3E08,
                0x3F4F,
                0x4800,
                0x5000,
                0x5700,
                0x5801,
                0x5900,
                0x5C01,
                0x5D41,
                0x6101,
                0x6201,
                0x6501,
                0x6861,
                0x6B00,
                0x6C01,
                0x6E88,
                0x7A00,
                0x7C00,
                0x7E00,
                0x7F00,
                0x8000,
                0x8100,
                0x9D01,
                0x5C00,
                0x16000,
                0x20001,
                0x20101,
                0x2020F,
                0x20301,
                0x20403,
                0x20500,
                0x20600,
                0x20700,
                0x2087D,
                0x20903,
                0x20F00,
                0x21000,
                0x211F2,
                0x2130F,
                0x27000,
                0x29A0F,
                0x29B04,
                0x29C1B,
                0x2C11F,
                0x2C27F,
                0x2C400,
                0x33000,
                0x33100,
                0x33200,
                0x33300,
                0x33400,
                0x33500,
                0x33600,
                0x33700,
                0x33800,
                0x33900,
                0x33A00,
                0x33B00,
                0x33C00,
                0x33D00,
                0x33E00,
                0x33F00,
                0x36000,
                0x36100,
                0x36200,
                0x36300,
                0x36400,
                0x36500,
                0x36600,
                0x36700,

                //25.02.17 for JMODE 10
                0x002B15, // EN_VA11_NOISE_SUPPR
                0x020000, // Clear JESD_EN (always before CAL_EN)
                0x006100, // Clear CAL_EN (always after JESD_EN)
                0x02010A, // Set JMODE10
                0x02021F, // Set KM1=31 so K=32
                0x020403, //0x020401, // Use SYNCSE input, offset binary data, scrambler enabled
                0x02130F, // Enable overrange, set overrange holdoff to max period 4*2^7 = 512 samples
                0x006101, // Set CAL_EN (always before JESD_EN)
                0x020001, // Set JESD_EN (always after CAL_EN)
                0x006C00, // Set CAL_SOFT_TRIG low to reset calibration state machine
                0x006C01, // Set CAL_SOFT_TRIG high to enable calibration
};

产品带壳测试的结果:

image.png

时钟芯片

image.png

image.png

image.png

  • 您好,

    已经收到了您的案例,调查需要些时间,感谢您的耐心等待。

  • 这个问题是否完全是由时钟芯片引起的?请帮忙将ADC配置与时钟信号分离——能否提供一个外部时钟信号,并确认ADC是否仍能按预期配置链路?

  • 麻烦说清楚,那个问题,如果是问题4,我们设置了输入时钟125M,N从8设置到10,使能TRIGOUT,测试到488M的输出,和156.25M N设置为8,测试到的时钟是一致的,读取 JESD STATUS Register(Address=0x208)[reset = 0x0]寄存器值

    正常版本156.25M N设置为8是0x00, 
    修改后的125M N设置为10是0xC0,

    FPGA那边是直接使用Xilinx的IP,你们的IP申请了还没有通过,如果可以麻烦看下为什么申请一直在Pending

  • 麻烦说清楚,那个问题,如果是问题4,我们设置了输入时钟125M,N从8设置到10,使能TRIGOUT,测试到488M的输出,和156.25M N设置为8,测试到的时钟是一致的,读取 JESD STATUS Register(Address=0x208)[reset = 0x0]寄存器值

    正常版本156.25M N设置为8是0x00, 
    修改后的125M N设置为10是0xC0,

    FPGA那边是直接使用Xilinx的IP,读取到的值全部一样是最大值,你们的IP申请了还没有通过,如果可以麻烦看下为什么申请一直在Pending