Part Number: DAC3484
我们的板子上只有一颗DAC3484。使用一个低抖动的时钟芯片产生两路时钟，一路为61.44M，送给FPGA.另一路为368.64M送给DAC3484的DACCLK输入。FPGA内部使用PLL将61.44倍频到368.64.使用DAC3484内部锁相环将输入的DACCLK 368.64倍频到737.28M。使用frame作为单同步源。2倍插值。操作时序是1、TXENABLE=0，SLEEP = 0，上电后复位100ms，2、配置所有的寄存器，3、提供DATACLK、DATA、FRAME（只发一次，不是周期性的，脉冲持续4个DATACLK）4、等待PLL锁定后，向config5 写0，然后读config5。读取到的config5一直为0x3940。也尝试了采用sif_sync以及双同步源模式（使用PLL产生的OSTR）都不行，都是报0x3940。寄存器配置如下，请帮忙分析一下什么问题。
{0x02,0xF0e2},
{0x00,0x029c},
{0x01,0x010E},
{0x03,0x9001},
{0x04,0x0000},
{0x05,0x0000},
{0x07,0x407F},
{0x09,0x8000},
{0x08,0x0000},
{0x0B,0x0000},
{0x0A,0x0000},
{0x0C,0x0400},
{0x0D,0x4400},
{0x10,0x0000},
{0x0E,0x0400},
{0x0F,0x0400},
{0x11,0x0000},
{0x14,0x0000},
{0x15,0x0000},
{0x12,0x0000},
{0x16,0x0000},
{0x17,0x0000},
{0x13,0x0000},
{0x18,0x2ce8},
{0x19,0x20f4},
{0x1A,0x9000},
{0x1B,0x0800},
{0x1E,0x8888},
{0x1F,0x8880},
{0x22,0x1B1B},
{0x23,0x005F},
{0x24,0x0000},
{0x2D,0x0004},
{0x2E,0x0000},
{0x2F,0x0000},
{0x30,0x2250},
{0x00,0xf19c},
{0x20,0x2201},
{0x05,0x0000},
