Part Number: AFE58JD28
Hello, we are currently attempting to integrate 8 afe58jd28 devices onto a single PCB. We are currently using subclass 1. Regarding the single afe device, what is the most ideal ramp test result? Does it need to ensure that the first valid data decoded by the FPGA after each link remains the same? Currently, the first ramp test data for each individual afe in our results is constantly changing and fluctuating between two sampling points. This makes it extremely difficult for me to establish a baseline for aligning the 8-device array.
Secondly, when debugging the 8 devices, do the 8 trig signals need to be of equal length?
Thirdly, does the processing of the 8 AFEs in accordance with the JESD204B standard need to be carried out within the same clock domain? Is it necessary to connect the sync signal line?
Looking forward to your reply very much.