AFE58JD28: Multiple AFE58JD28 devices synchronization and link establishment repeatability

Part Number: AFE58JD28

Hello, we are currently attempting to integrate 8 afe58jd28 devices onto a single PCB. We are currently using subclass 1. Regarding the single afe device, what is the most ideal ramp test result? Does it need to ensure that the first valid data decoded by the FPGA after each link remains the same? Currently, the first ramp test data for each individual afe in our results is constantly changing and fluctuating between two sampling points. This makes it extremely difficult for me to establish a baseline for aligning the 8-device array.
Secondly, when debugging the 8 devices, do the 8 trig signals need to be of equal length?
Thirdly, does the processing of the 8 AFEs in accordance with the JESD204B standard need to be carried out within the same clock domain? Is it necessary to connect the sync signal line?
Looking forward to your reply very much.

  • 您好,
    已经收到了您的案例,调查需要些时间,感谢您的耐心等待。

  • Hello, this issue has been bothering us for a long time. Currently, the main problem is that the first valid data value after decoding with 8 pieces of chips fluctuates, and the 8 pieces cannot guarantee that the first valid data is the same, which will cause deviations in the subsequent data, as shown in the following figure. We have used trig before each link establishment and performed the synchronization operation on the 8 pieces.
    ...

  • 你好,

    1. 每次链路建立时,斜坡测试模式的结果都可能发生变化。而且,对于不同的AFE,结果也可能不同。因此,您的观察是正确的。为了确保多个AFE在链路建立时具有一致的斜坡模式相位,必须同时向所有8个AFE施加TX_TRIG信号。

    2. 为了同步所有AFE并保持一致的斜坡模式相位,必须同时对所有AFE施加TX_TRIG信号。TX_TRIG信号的长度无关紧要,重要的是其上升沿。所有AFE必须同时接收到该上升沿。TX_TRIG信号用于重置斜坡模式的相位,并用于同步多个AFE。应在JESD链路建立后施加该信号,以确保所有AFE同步。

    3. 如果您使用的是 JESD 子类 1 标准,则必须将 SYSREF 应用于所有 AFE,并且 SYSREF 信号到每个 AFE 的路由长度应匹配,以确保链路建立正确。