工程师，你好。我现在使用THS8200来产生VGA信号，我输入的数据是4：2：2，60HZ,720P信号。我现在遇到两个问题！我的IIC为什么能够配置一些寄存器，有些寄存器配置不来。器件地址和寄存器地址应答，写入数据，偶尔不应答，总线上其他的IIC器件都没有问题。我的配置如下，谢谢。
errors = THS8200_WR(0x40, 0x03, 0x01); // chip_ctl
errors = THS8200_WR(0x40, 0x04, 0x81); //csc_ric1
errors = THS8200_WR(0x40, 0x05, 0xD5); //csc_rfc1
errors = THS8200_WR(0x40, 0x06, 0x00); //csc_ric2
errors = THS8200_WR(0x40, 0x07, 0x00); //csc_rfc2
errors = THS8200_WR(0x40, 0x08, 0x06); //csc_ric3
errors = THS8200_WR(0x40, 0x09, 0x29); //csc_rfc3
errors = THS8200_WR(0x40, 0x0A, 0x04); //csc_gic1
errors = THS8200_WR(0x40, 0x0B, 0x00); //csc_gfc1
errors = THS8200_WR(0x40, 0x0C, 0x04); //csc_gic2
errors = THS8200_WR(0x40, 0x0D, 0x00); //csc_gfc2
errors = THS8200_WR(0x40, 0x0E, 0x04); //csc_gic3
errors = THS8200_WR(0x40, 0x0F, 0x00); //csc_gfc3
errors = THS8200_WR(0x40, 0x10, 0x80); //csc_bic1
errors = THS8200_WR(0x40, 0x11, 0xBB); //csc_bfc1
errors = THS8200_WR(0x40, 0x12, 0x07); //csc_bic2
errors = THS8200_WR(0x40, 0x13, 0x42); //csc_bfc2
errors = THS8200_WR(0x40, 0x14, 0x00); //csc_bic3
errors = THS8200_WR(0x40, 0x15, 0x00); //csc_bfc3
errors = THS8200_WR(0x40, 0x16, 0x14); //csc_offset1
errors = THS8200_WR(0x40, 0x17, 0xAE); //csc_offset12
errors = THS8200_WR(0x40, 0x18, 0x8B); //csc_offset23
errors = THS8200_WR(0x40, 0x19, 0x15); //csc_offset3
errors = THS8200_WR(0x40, 0x1C, 0x53); //dman_cntl 20bit 422
//sync tip and horizontal blank level setup
errors = THS8200_WR(0x40, 0x1D, 0x00); //dtg_y_sync1
errors = THS8200_WR(0x40, 0x1E, 0x00); //dtg_y_sync2
errors = THS8200_WR(0x40, 0x1F, 0x00); //dtg_y_sync3
errors = THS8200_WR(0x40, 0x20, 0x00); //dtg_cbcr_sync1
errors = THS8200_WR(0x40, 0x21, 0x00); //dtg_cbcr_sync2
errors = THS8200_WR(0x40, 0x22, 0x00); //dtg_cbcr_sync3
errors = THS8200_WR(0x40, 0x23, 0x2A); //dtg_y_sync_upper
errors = THS8200_WR(0x40, 0x24, 0x00); //dtg_cbcr_sync_upper
//horizontal timing setup
errors = THS8200_WR(0x40, 0x25, 0x60); // dtg_spec_a 96
errors = THS8200_WR(0x40, 0x26, 0x0E); // dtg_spec_b Hfp-2 (16-2)
errors = THS8200_WR(0x40, 0x27, 0x00); // dtg_spec_c
errors = THS8200_WR(0x40, 0x28, 0x90); // dtg_spec_d 144
errors = THS8200_WR(0x40, 0x29, 0x00); // dtg_spec_d1
errors = THS8200_WR(0x40, 0x2A, 0x00); // dtg_spec_e
errors = THS8200_WR(0x40, 0x2B, 0x00); // dtg_spec_h_msb
errors = THS8200_WR(0x40, 0x2C, 0x00); // dtg_spec_h_lsb
errors = THS8200_WR(0x40, 0x2D, 0x00); // dtg_spec_i_msb
errors = THS8200_WR(0x40, 0x2E, 0x00); // dtg_spec_i_lsb
errors = THS8200_WR(0x40, 0x2F, 0x0E); // dtg_spec_k_lsb 16-2
errors = THS8200_WR(0x40, 0x30, 0x00); // dtg_spec_k_msb
errors = THS8200_WR(0x40, 0x31, 0x00); // dtg_spec_k1
errors = THS8200_WR(0x40, 0x32, 0x00); // dtg_speg_g_lsb
errors = THS8200_WR(0x40, 0x33, 0x00); // dtg_speg_g_msb
errors = THS8200_WR(0x40, 0x34, 0x03); // dtg_total_pixel_msb //800 pixels
errors = THS8200_WR(0x40, 0x35, 0x20); // dtg_total_pixel_lsb
errors = THS8200_WR(0x40, 0x36, 0x00); // dtg_linecnt_msb
errors = THS8200_WR(0x40, 0x37, 0x01); // dtg_linecnt_lsb
errors = THS8200_WR(0x40, 0x38, 0x89); // dtg_mode Generic SDTV
errors = THS8200_WR(0x40, 0x39, 0x22); // dtg_frame_field_msb //525 lines
errors = THS8200_WR(0x40, 0x3A, 0x0D); // dtg_frame_size_lsb
errors = THS8200_WR(0x40, 0x3B, 0x0D); // dtg_field_size_lsb
errors = THS8200_WR(0x40, 0x3C, 0x80); // dtg_vesa_cbar_size
//CSM setup to map YCbCr to FS RGB
errors = THS8200_WR(0x40, 0x41, 0x40); // csm_clip_gy_low
errors = THS8200_WR(0x40, 0x42, 0x40); // csm_clip_bcb_low
errors = THS8200_WR(0x40, 0x43, 0x40); // csm_clip_rcr_low
errors = THS8200_WR(0x40, 0x44, 0x53); // csm_clip_gy_high
errors = THS8200_WR(0x40, 0x45, 0x3F); // csm_clip_bcb_high
errors = THS8200_WR(0x40, 0x46, 0x3F); // csm_clip_rcr_high
errors = THS8200_WR(0x40, 0x47, 0x40); // csm_shift_gy
errors = THS8200_WR(0x40, 0x48, 0x40); // csm_shift_bcb
errors = THS8200_WR(0x40, 0x49, 0x40); // csm_shift_rcr
errors = THS8200_WR(0x40, 0x4A, 0xFC); // csm_mult_gy_msb
errors = THS8200_WR(0x40, 0x4B, 0x44); // csm_mult_bcb_rcr_msb
errors = THS8200_WR(0x40, 0x4C, 0xAC); // csm_mult_gy_lsb
errors = THS8200_WR(0x40, 0x4D, 0xAC); // csm_mult_bcb_lsb
errors = THS8200_WR(0x40, 0x4E, 0xAC); // csm_mult_rcr_lsb
errors = THS8200_WR(0x40, 0x4F, 0xFF); // csm_mode
//Generic Mode Line Type Setup. Set dtg_bp 2_msb and lsb to 526 (lines per frame +1)
errors = THS8200_WR(0x40, 0x50, 0x02); // dtg_bp1_2_msb
errors = THS8200_WR(0x40, 0x58, 0x00); // dtg_bp1_lsb
errors = THS8200_WR(0x40, 0x59, 0x0E); // dtg_bp2_lsb
errors = THS8200_WR(0x40, 0x68, 0x00); // dtg_linetype1 = active video
errors = THS8200_WR(0x40, 0x69, 0x00); // dtg_linetype2 = active vieo
errors = THS8200_WR(0x40, 0x70, 0x60); // dtg_hlength_lsb HS=96
errors = THS8200_WR(0x40, 0x71, 0x00); // dtg_hdly_msb
errors = THS8200_WR(0x40, 0x72, 0x01); // dtg_hdly_lsb
errors = THS8200_WR(0x40, 0x73, 0x03); // dtg_vlength_lsb VS=2+1
errors = THS8200_WR(0x40, 0x74, 0x00); // dtg_vdly_msb
errors = THS8200_WR(0x40, 0x75, 0x01); // dtg_vdly_lsb
errors = THS8200_WR(0x40, 0x76, 0x00); // dtg_vlength2_lsb
errors = THS8200_WR(0x40, 0x77, 0x07); // dtg_vdly2_msb
errors = THS8200_WR(0x40, 0x78, 0xFF); // dtg_vdly2_lsb
errors = THS8200_WR(0x40, 0x79, 0x00); // dtg_hs_in_dly_msb
errors = THS8200_WR(0x40, 0x7A, 0x38); // dtg_hs_in_dly_lsb 40+Hfp =40+16=56
errors = THS8200_WR(0x40, 0x7B, 0x00); // dtg_vs_in_dly_msb
errors = THS8200_WR(0x40, 0x7C, 0x0A); // dtg_vs_in_dly_lsb Vfp=10
errors = THS8200_WR(0x40, 0x82, 0x23); // pol_cntl -HS -VS 同步信号控制（输入为嵌入式同步）