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spec要求时钟clk和ser的信号建立时间在3.3v供电是需要大于5ns，但是由于硬件设计原因，导致时钟clk和ser信号的在上升沿是同时触发，请问会不会造成误采样? 如果造成误采样的话，是不是只能通过延时clk的方法来确保采样ser正确？
