TI工程师您好：
设计电路按照ADS5402EVM开发板设计，使用三片ADS5404进行6通道同步采集，采样结果发现有一定的概率出现某个通道和其他5个通道的相位差了2个cycle，但是我接收回来的SYNCOUT信号相位却是一致的，请问这是什么原因造成的呢？我记得此ADC可以支持交织模式，是否与寄存器配置有关系呢？
附：寄存器设置：
reg [15:0] CFG_REG0 = 16'hD2F0; //addr 0x2C RESET SPI
reg [15:0] CFG_REG1 = 16'h8206; //addr 0x01 ENABLE A/B CH GAIN/OFFSET;
//TWO'COMPLEMENT DATA;
//HIGH PERFORMANCE MODE
reg [15:0] CFG_REG4 = 16'h8000; //addr 0x00 4 WIRE SPI
reg [15:0] CFG_REG5 = 16'h0780; //addr 0x02 SET OVER-RANGE THRESHOLD
reg [15:0] CFG_REG6 = 16'hAAA8; //*//addr 0x0E SYNC DRIVED FROM SYNC PINS
reg [15:0] CFG_REG7 = 16'hA010; //*//addr 0x0F SYNC DRIVED FROM SYNC PINS;VREF SEL-1.25V
reg [15:0] CFG_REG8 = 16'hFFDF; //addr 0x38 HP MODE;INT BIAS;SYNC BUF DISABLED;INPUT BUF DIASBALED
reg [15:0] CFG_REG9 = 16'hDE1B; //addr 0x3A
reg [15:0] CFG_REGA = 16'h2FFF; //addr 0x66 NOT USED PINS PD;DA11-DA0 enable
reg [15:0] CFG_REGB = 16'h2FFF; //addr 0x67 NOT USED PINS PD;DB11-DB0 enable
reg [15:0] CFG_REG2 = 16'h4B18; //addr 0x03/0x1A CLEAR ACCUMULATOR VALUES
reg [15:0] CFG_REG3 = 16'h0B18; //addr 0x03/0x1A START DC AND AUTO-CORRECTION LOOP
