This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
应用环境:Intel FPGA+ADS7865完成模拟电路采集
问题1:除了参数手册外,是否有更详尽的软件代码案例。Verilog如何编写ADS7865的相关代码?
问题2:此芯片可实现3+3伪差分或者2+2全差分的采样,最高可实现2M采样率。但是在3+3模式2M采样率下,数据能否保持同步传输?能否实现数据的及时读取?
问题3:3+3模式下,能否每次只读上3路数据,忽略下3路?(能否实现6路采集,但只读取某几路?)