TSW14J57EVM: Setup_TSW14J57ADCFirmware.exe 安装的工程，编译生成的版本文件，提示READ_REGISTER_FAILED 错误

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Part Number: TSW14J57EVM

Setup_TSW14J57ADCFirmware.exe 安装后，编译相应的工程；生成的版本文件，通过 High Speed Data Converter Pro 下载到 TSW14J57EVM 之后，提示 READ_REGISTER_FAILED 错误。什么原因导致了这个错误？

7 个月前

0 Amy Luo 6 个月前

TI__Guru**** 185470 points

您好，

今天我休假了，明天我会具体看下您的问题，很抱歉给您造成不便。

0 Amy Luo 6 个月前

TI__Guru**** 185470 points

HSDC Pro 是否识别到了 TSW14J57EVM

0 ?? ? 6 个月前

Prodigy 10 points

能够识别到TSW14J57EVM。ini 文件内容如下：

[ADC]

\\ LMF = 4841
\\ 8 ADC's, 2 ADC's per lane (I & Q)
\\ Fs = 500MHz, each ADC clocked at 250MHz
\\ Lane rate = 250 * 10 * 4 = 10Gbps
Interface name="output_file"
Number of channels=8
Channel Pattern=8,7,6,5,4,3,2,1

Data Postprocessing=1:32768
\\operation:operand
\\operaion
\\0=bit shift
\\1=xor
\\2=and
\\3=or
\\4=not
\\operand
\\value(+ve if bitshift by right and -ve if bitshift by left)
\\E.g 0:-2,1:1024
\\bitshift by left 2 times and then xor by 1024
Number of Bits=16
Max sample Rate=500000000
Register_Config="-"
\\[Register Address]:[Register Value]:[Number of Bytes to be sent as]
DLL Version=1.0
Read EVM Setup Procedure="EVM Setup Procedure not available"
\\use <> as delimiter for newline

[Version 1.0]

JESD IP Core_CS=0
JESD IP Core_F=4
JESD IP Core_HD=0
JESD IP Core_K=16
JESD IP Core_L=4
JESD IP Core_M=8
JESD IP Core_N=16
JESD IP Core_NTotal=16
JESD IP Core_S=1
JESD IP Core_SCR=0
JESD IP Core_Tailbits=0
JESD IP Core_LaneSync=1
JESD IP Core_Subclass=1
MIF Config= 0.611G to 0.7G:RX:RX_PMA_x5,0.7G to 3.125G:RX:RX_PMA_x10,3.125G to 10.25G:RX:RX_PMA_x40
\\List of Lane Rate Range,PLL Type and their MIF File names that needs to be configured,separated by ":"
\\These MIF Files need to be present under MIF Files Folder
Fabric PLL Counter = 0.611G to 0.7G:0x081010,0.7G to 3.125G:0x080808,3.125G to 10.25G:0x080202
Invert Sync Polarity = 0
\\Invert Sync polarity, 1:invert; 0: do not invert
Invert Serdes Data = 0
\\Invert Serdes Data, 1:invert; 0: do not invert
Transceiver Mode = 0
\\1:xcvr mode; 0: TX/RX only mode

Lane Mapping=lane0:3,lane1:2,lane2:1,lane3:0

Group 128 bits Flag = 1
\\If 1, will group 128 bits from each DDR, and then apply the channel pattern
\\If this parameter is not present, it will follow the earlier mode used in v2.40
Bit Packing = 1
\\0 - Data are not bit packed.
\\1 - Data are bit packed(MSB aligned) without any padded zeroes

Bit Packing Channel Pattern = C1S1[15:8],C1S1[7:0],C2S1[15:8],C2S1[7:0],C3S1[15:8],C3S1[7:0],C4S1[15:8],C4S1[7:0],C5S1[15:8],C5S1[7:0],C6S1[15:8],C6S1[7:0],C7S1[15:8],C7S1[7:0],C8S1[15:8],C8S1[7:0]

\\ With F=1, sample from every other lane.
\\ With F=2, take 4 samples from lane 0, then 4 from lane 1, 4 from lane 2, ect....