Hi TI’s expert,
I am now using 4-DDC2256A along with Xilinx Artix-7 FPGA for CT detector developing. I had several questions when I layout the PCB.
Q1: How do we connect to the differential clock inputs (CLK) and CONV of the device between FPGA and four DDC2256As? Star pattern? Daisy chain pattern? Individual pattern? Which pattern is the best? Now, in the first version, we use the individual pattern.
Q2: We now have 1024 signals from photon diodes array, should we shield the signals with QGND? As in our first version, the noise of every channel seems too high.
Q3: Sometimes, when we acquire the date from DDC2256A, we will first get normal data, then 0, then normal data, and then 0 again, it will keep circulating. This phenomenon is especially serious in the low range(6.25pc, 12.5pc……).
